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general description the max5965a/max5965b are quad, monolithic, -48v power controllers designed for use in ieee ? 802.3af-com- pliant/ieee 802.3at-compatible power-sourcing equipment (pse). these devices provide powered device (pd) dis- covery, classification, current limit, dc and ac load discon- nect detections in compliance with the ieee 802.3af standard. the max5965a/max5965b are pin compatible with the max5952/max5945/ltc4258/ltc4259a pse controllers and provide additional features. the max5965a/max5965b feature a high-power mode that provides up to 45w per port. the max5965a/ max5965b provide new class 5 and 2-event classifica- tion (class 6) for detection and classification of high- power pds. the max5965a/max5965b provide instantaneous readout of each port current through the i 2 c interface. the max5965a/max5965b also provide high-capacitance detection for legacy pds. these devices feature an i 2 c-compatible, 3-wire serial inter- face, and are fully software configurable and programmable. the class-overcurrent detection function enables system power management to detect if a pd draws more than the allowable current. the max5965a/max5965bs extensive programmability enhances system flexibility, enables field diagnosis, and allows for uses in other applications. the max5965a/max5965b provide four operating modes to suit different system requirements. auto mode allows the devices to operate automatically without any software supervision. semi-automatic mode automatically detects and classifies a device connected to a port after initial software activation, but does not power up that port until instructed to by software. manual mode allows total soft- ware control of the device and is useful for system diag- nostics. shutdown mode terminates all activities and securely turns off power to the ports. the max5965a/max5965b provide input undervoltage lockout (uvlo), input undervoltage detection, a load- stability safety check during detection, input overvolt- age lockout, overtemperature detection, output voltage slew-rate limit during startup, power-good status, and fault status. the max5965a/max5965bs programma- bility includes startup timeout, overcurrent timeout, and load-disconnect detection timeout. the max5965a/max5965b are available in a 36-pin ssop package and are rated for both extended (-40c to +85c) and upper commercial (0c to +85c) temperature ranges. applications power-sourcing equipment (pse) switches/routers midspan power injectors features ieee 802.3af compliant/ieee 802.3at compatible instantaneous readout of port current through i 2 c interface high-power mode enables up to 45w per port high-capacitance detection for legacy devices pin compatible with max5952/max5945/ ltc4258/ltc4259a four independent power-switch controllers pd detection and classification (including 2- event classification) selectable load-stability safety check during detection supports both dc and ac load removal detections i 2 c-compatible, 3-wire serial interface current foldback and duty-cycle-controlled current limit open-drain int signal direct fast shutdown control capability special class 5 classification max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ________________________________________________________________ maxim integrated products 1 19-4593; rev 3; 3/12 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. ordering information part temp range pin-package max5965a eax+ -40c to +85c 36 ssop max5965auax+* 0c to +85c 36 ssop max5965b eax+ -40c to +85c 36 ssop max5965buax+* 0c to +85c 36 ssop + denotes a lead(pb)-free/rohs-compliant package. * future productcontact factory for availability. ieee is a registered service mark of the institute of electrical and electronics engineers, inc. selector guide part pin-package ac disconnect feature max5965aeax+ 36 ssop no max5965auax+ 36 ssop no max5965beax+ 36 ssop yes max5965buax+ 36 ssop yes
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v agnd = 32v to 60v, v ee = 0v, v dd to v dgnd = +3.3v, all voltages are referenced to v ee , unless otherwise noted. typical values are at v agnd = +48v, v dgnd = +48v, v dd = (v dgnd + 3.3v), t a = +25c. currents are positive when entering the pin and negative other- wise.) (note 2) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (voltages referenced to v ee , unless otherwise noted.) agnd, dgnd, det_, v dd , reset , a3Ca0, shd_ , osc, scl, sdain, auto .............................................-0.3v to +80v out_........................................................-12v to (agnd + 0.3v) gate_ (internally clamped) (note 1) ..................-0.3v to +11.4v sense_ ..................................................................-0.3v to +24v v dd , reset , midspan, a3Ca0, shd_ , osc, scl, sdain and auto to dgnd ..................................-0.3v to +7v int and sdaout to dgnd....................................-0.3v to +12v maximum current into int , sdaout, det_ .......................80ma maximum power dissipation (t a = +70c) 36-pin ssop (derate 17.4mw/c above +70c) .....1388.9mw operating temperature ranges: max5965a/max5965b_eax ...-40c to +85c max5965a/max5965b_uax ...............................0c to +85c storage temperature range .............................-65c to +150c junction temperature ......................................................+150c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c note 1: gate_ is internally clamped to 11.4v above v ee . driving gate_ higher than 11.4v above v ee may damage the device. parameter symbol conditions min typ max units power supplies v agnd v agnd - v ee 32 60 v dgnd 060 v dd to v dgnd , v dgnd = v agnd 2.4 3.6 operating voltage range v dd v dd to v dgnd , v dgnd = v ee 3.0 3.6 v i ee v out_ = v ee , v sense _ = v ee , det _ = agnd, all logic inputs open, scl = sdain = v dd . int and sdaout unconnected. measured at agnd in power mode after gate_ pullup 4.8 6.8 supply currents i dig all logic inputs high, measured at v dd 0.2 0.4 ma gate driver and clamping gate_ pullup current i pu power mode, gate drive on, v gate_ = v ee (note 3) -40 -50 -65 a weak gate_ pulldown current i pdw shd_ = dgnd, v gate_ = v ee + 10v 42 a maximum pulldown current i pds v sense_ = 600mv, v gate_ = v ee + 2v 100 ma external gate drive v gs v gate_ - v ee , power mode, gate drive on, i pu = 1a 9 10 11.5 v
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet _______________________________________________________________________________________ 3 electrical characteristics (continued) (v agnd = 32v to 60v, v ee = 0v, v dd to v dgnd = +3.3v, all voltages are referenced to v ee , unless otherwise noted. typical values are at v agnd = +48v, v dgnd = +48v, v dd = (v dgnd + 3.3v), t a = +25c. currents are positive when entering the pin and negative other- wise.) (note 2) parameter symbol conditions min typ max units current limit ivee = 00 202 212 220 ivee = 01 192 202 212 ivee = 10 186 190 200 current-limit clamp voltage v su_lim m axi m um v s e n s e _ al l ow ed d ur i ng cur r ent l i m i t, v ou t_ = 0v (icut = 000) (note 4) ivee = 11 170 180 190 mv icut = 000 (class 0/3) 177 186 196 icut = 110 (class 1) 47 55 64 icut = 111 (class 2) 86 94 101 icut = 001 265 280 295 icut = 010 310 327 345 icut = 011 355 374 395 icut = 100 398 419 440 overcurrent threshold after startup v flt_lim overcurrent v sense_ threshold allowed for t t fault after startup; v out_ = 0v (ivee = 00) icut = 101 443 466 488 mv icut = 000, icut = 110, icut = 111 32 foldback initial out_ voltage v flbk_st v out_ - v ee , above which the current-limit trip voltage starts folding back, ivee = 00 icut = 001101 13 v foldback final out_ voltage v flbk_end ivee = 00, icut = 000, v out_ - v ee above which the current-limit trip voltage reaches v th_fb 50 v minimum foldback current-limit threshold v th_fb v out_ = agnd = 60v, ivee = 00, icut = 000 64 mv sense_ input bias current v sense_ = v ee -5 +5 a
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 4 _______________________________________________________________________________________ electrical characteristics (continued) (v agnd = 32v to 60v, v ee = 0v, v dd to v dgnd = +3.3v, all voltages are referenced to v ee , unless otherwise noted. typical values are at v agnd = +48v, v dgnd = +48v, v dd = (v dgnd + 3.3v), t a = +25c. currents are positive when entering the pin and negative other- wise.) (note 2) parameter symbol conditions min typ max units supply monitors v ee undervoltage lockout v eeuvlo v agnd - v ee , v agnd - v ee increasing 28.5 v v ee undervoltage lockout hysteresis v eeuvloh p or ts shut d ow n i f v agnd - v e e < v u v l o - v e e u v l oh 3v v ee overvoltage lockout v ee_ov v ee_ov event bit sets and ports shut down if v agnd - v ee > v ee_ov , v agnd increasing 62.5 v v ee overvoltage lockout hysteresis v ovh 1v v ee undervoltage v ee_uv v e e _ u v event b i t i s set i f v agnd - v e e < v e e _ u v , v e e i ncr easi ng 40 v v dd overvoltage v dd_ov v dd_ov event bit is set if v dd - v dgnd > v dd_ov ; v dd increasing 3.82 v v dd undervoltage v dd_uv v dd_uv is set if v dd - v dgnd < v dd_uv , v dd decreasing 2.7 v v dd undervoltage lockout v dduvlo device operates when v dd - v dgnd > v dduvlo , v dd increasing 2v v dd undervoltage lockout hysteresis v ddhys 120 mv thermal shutdown threshold t shd ports shut down and device resets if its junction temperature exceeds this limit, temperature increasing (note 5) +150 c thermal shutdown hysteresis t shdh thermal hysteresis, temperature decreasing (note 5) 20 c output monitor out_ input current i bout v out_ = v agnd , all modes 2 a idle pullup current at out_ i dis out_ discharge current, detection and classification off, port shutdown, v out_ = agnd - 2.8v 200 265 a pgood high threshold pg th v out_ - v ee , v out_ decreasing 1.5 2.0 2.5 v pgood hysteresis pg hys 220 mv pgood low-to-high glitch filter t pgood minimum time pgood has to be high to set bit in register 10h 3ms
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet _______________________________________________________________________________________ 5 electrical characteristics (continued) (v agnd = 32v to 60v, v ee = 0v, v dd to v dgnd = +3.3v, all voltages are referenced to v ee , unless otherwise noted. typical values are at v agnd = +48v, v dgnd = +48v, v dd = (v dgnd + 3.3v), t a = +25c. currents are positive when entering the pin and negative other- wise.) (note 2) parameter symbol conditions min typ max units load disconnect dc load disconnect threshold v dcth minimum v sense_ allowed before disconnect (dc disconnect active), v out_ = 0v 2.5 3.75 5.0 mv ac load disconnect threshold i acth current into det_, for i < i acth the port powers off, acd_en_ bit = h; v osc = 2.2v, max5965b (note 6) 285 320 360 a oscillator buffer gain a osc v det_ /v osc , acd_en_ bit = h, max5965b 2.9 3.0 3.1 v/v osc fail threshold v osc_fail port does not power on if v osc < v osc_fail and acd_en_ bit is high, max5965b (note 7) 1.8 2.2 v osc input impedance z osc osc input impedance when all the acd_en_ are active, max5965b 100 k ? load disconnect timer t disc time from v sense_ < v dcth to gate shutdown (note 8) 300 400 ms detection detection probe voltage (first phase) v dph1 v agnd - v det_ during the first detection phase 3.8 4 4.2 v detection probe voltage (second phase) v dph2 v agnd - v det_ during the second detection phase 9.0 9.3 9.6 v current-limit protection i dlim v det_ = v agnd , during detection, measure current through det_ 1.5 1.8 2.2 ma short-circuit threshold v dcp if v agnd - v out_ < v dcp after the first detection phase a short circuit to agnd is detected 1v open-circuit threshold i d_open first point measurement current threshold for open condition 12.5 a resistor detection window r dok (note 9) 19.0 26.5 k ? detection rejects lower values 15.2 resistor rejection window r dbad detection rejects higher values 32 k ?
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 6 _______________________________________________________________________________________ electrical characteristics (continued) (v agnd = 32v to 60v, v ee = 0v, v dd to v dgnd = +3.3v, all voltages are referenced to v ee , unless otherwise noted. typical values are at v agnd = +48v, v dgnd = +48v, v dd = (v dgnd + 3.3v), t a = +25c. currents are positive when entering the pin and negative other- wise.) (note 2) parameter symbol conditions min typ max units digital inputs/outputs (referred to dgnd) digital input low v il 0.9 v digital input high v ih 2.4 v internal input pullup/pulldown resistor r din pullup (pulldown) resistor to v dd (dgnd) to set default level 25 50 75 k ? o p en- d r ai n o utp ut low v ol tag ev ol i sink = 15ma 0.4 v digital input leakage i dl input connected to the pull voltage 2 a open-drain leakage i ol open-drain high impedance, v out_ = 3.3v 2 a timing startup time t start time during which a current limit set by v su_lim is allowed, starts when the gate_ is turned on (note 9) 50 60 70 ms fault time t fault maximum allowed time for an overcurrent condition set by v flt_lim after startup (note 9) 50 60 70 ms port turn-off time t off minimum delay between any port turning off, does not apply in case of a reset 0.5 ms detection reset time time allowed for the port voltage to reset before detection starts 80 90 ms detection time t det maximum time allowed before detection is completed 330 ms m i d sp an m od e d etecti on d el ay t dmid 2.0 2.4 s classification time t class time allowed for classification 19 23 ms v eeuvlo turn-on delay t dly time v agnd must be above the v eeuvlo thresholds before the device operates 24ms rstr bits = 00 16 x t fault rstr bits = 01 32 x t fault rstr bits = 10 64 x t fault restart timer t restart time a port has to wait before turning on after an overcurrent fault during normal operation, rstr_en bits = high rstr bits = 11 0 ms watchdog clock period t wd rate of decrement of the watchdog timer 164 ms adc performance resolution 9 bits range 0.51 v lsb step size 1mv integral nonlinearity (relative) inl 0.2 1.5 lsb
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet _______________________________________________________________________________________ 7 electrical characteristics (continued) (v agnd = 32v to 60v, v ee = 0v, v dd to v dgnd = +3.3v, all voltages are referenced to v ee , unless otherwise noted. typical values are at v agnd = +48v, v dgnd = +48v, v dd = (v dgnd + 3.3v), t a = +25c. currents are positive when entering the pin and negative other- wise.) (note 2) parameter symbol conditions min typ max units differential nonlinearity dnl 0.2 1.5 lsb gain error 3% adc absolute accuracy v sense_ = 300mv 295 300 305 lsb timing characteristics (for 2-wire fast mode) serial-clock frequency f scl 400 khz bus free time between a stop and start condition t buf 1.2 s hold time for a start condition t hd , sta 0.6 s low period of the scl clock t low 1.2 s high period of the scl clock t high 0.6 s setup time for a repeated start condition t su , sta 0.6 s data hold time t hd , dat 100 300 ns data in setup time t su , dat 100 ns rise time of both sda and scl signals, receiving t r 20 + 0.1c b 300 ns fall time of sda transmitting t f 20 + 0.1c b 300 ns setup time for stop condition t su , sto 0.6 s capacitive load for each bus line c b 400 pf pulse width of spike suppressed t sp 50 ns note 2: limits to t a = -40c are guaranteed by design. note 3: default values. the charge/discharge currents are programmable through the serial interface (see the register map and description section). note 4: default values. the current-limit thresholds are programmed through the i 2 c-compatible serial interface (see the register map and description section). note 5: functional test is performed over thermal shutdown entering test mode. note 6: this is the default value. threshold can be programmed through serial interface r23h[2:0]. note 7: ac disconnect works only if (v dd - v dgnd ) 3v and dgnd is connected to agnd. note 8 :t disc can also be programmed through the serial interface (r16h) (see the register map and description section). note 9: r d = (v out2 - v out1 )/(i det2 - i det1 ). v out1 , v out2 , i det2 , and i det1 represent the voltage at out_ and the current at det_ during phase 1 and 2 of the detection. note 10: default values. the startup and fault times can also be programmed through the i 2 c serial interface (see the register map and description section).
sense_ trip voltage vs. input voltage max5965a toc09 v agnd - v ee (v) sense_ trip voltage (mv) 56 52 36 40 44 48 185.5 186.0 186.5 187.0 187.5 188.0 188.5 189.0 185.0 32 60 max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 8 _______________________________________________________________________________________ typical operating characteristics (v ee = -48v, v dd = +3.3v, v auto = v agnd = v dgnd = 0v, reset = shd_ = unconnected, r sense_ = 0.5 ? , ivee = 00, icut = 000, t a = +25c, all registers = default setting, unless otherwise noted.) analog supply current vs. input voltage max5965a toc01 v agnd - v ee (v) supply current (ma) 56 52 44 48 40 36 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 4.5 32 60 measured at agnd analog supply current vs. temperature max5965a toc02 temperature ( n c) supply current (ma) 60 35 10 -15 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 4.5 -40 85 v ee = -32v v ee = -60v v ee = -48v digital supply current vs. temperature max5965a toc03 temperature ( n c) supply current ( f a) 60 35 10 -15 105 110 115 120 125 130 100 -40 85 v dd = 2.4v v dd = 3.3v v dd = 3.6v measured at v dd digital supply current vs. digital supply voltage max5965a toc04 supply voltage (v) supply current ( f a) 3.4 3.2 3.0 2.8 2.6 105 110 115 120 125 130 100 2.4 3.6 measured at v dd v ee undervoltage lockout vs. temperature max5965a toc05 temperature ( n c) undervoltage lockout (v) 60 35 10 -15 27.5 28.0 28.5 29.0 29.5 30.0 27.0 -40 85 gate_ overdrive vs. input voltage max5965a toc06 v agnd - v ee (v) gate_ overdrive (v) 56 52 44 48 40 36 9.92 9.94 9.96 9.98 10.00 10.02 10.04 10.06 10.08 10.10 9.90 32 60 gate_ overdrive vs. temperature max5965a toc07 temperature ( n c) gate_ overdrive (v) 60 35 -15 10 9.85 9.90 9.95 10.00 10.10 10.05 10.15 10.20 9.80 -40 85 sense_ trip voltage vs. temperature max5965a toc08 temperature ( n c) sense_ trip voltage (mv) 60 35 10 -15 184 188 192 196 180 -40 85
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet _______________________________________________________________________________________ 9 foldback current-limit threshold vs. output voltage max5965a toc10 v out_ - v ee (v) v sense_ - v ee (mv) 50 40 30 20 10 50 100 150 200 250 300 0 0 foldback current-limit threshold vs. output voltage max5965a toc10a v out_ - v ee (v) v sense_ - v ee (mv) 50 40 30 20 10 50 100 150 200 250 300 350 400 450 500 0 0 icut = 001 icut = 001 dc load disconnect threshold vs. temperature max5965a toc11 temperature ( n c) dc load disconnect threshold (mv) 60 35 10 -15 3 4 5 6 2 -40 85 overcurrent timeout (r load = 240 ? to 57 ? ) max5965a toc12 20ms/div v agnd - v out 50v/div i out_ 200ma/div int 5v/div v gate_ 10v/div 0v 0a 0v v ee overcurrent response waveform (max5965auax) (r load = 240 ? to 57 ? ) max5965a toc13 400 s/div v agnd - v out 50v/div i out_ 200ma/div int 2v/div v gate_ 10v/div 0v 0a 0v v ee short-circuit response time max5965a toc14 20ms/div v agnd - v out 20v/div i out_ 200ma/div v gate_ 10v/div 0v 0a v ee short-circuit response time max5965a toc15 4 s/div v agnd - v out 20v/div i out_ 10a/div v gate_ 10v/div 0v 130ma v ee typical operating characteristics (continued) (v ee = -48v, v dd = +3.3v, v auto = v agnd = v dgnd = 0v, reset = shd_ = unconnected, r sense_ = 0.5 ? , ivee = 00, icut = 000, t a = +25c, all registers = default setting, unless otherwise noted.)
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 10 ______________________________________________________________________________________ typical operating characteristics (continued) (v ee = -48v, v dd = +3.3v, v auto = v agnd = v dgnd = 0v, reset = shd_ = unconnected, r sense_ = 0.5 ? , ivee = 00, icut = 000, t a = +25c, all registers = default setting, unless otherwise noted.) reset to out turn-off delay max5965a toc16 0v 0a i out_ 200ma/div v gate_ 5v/div v ee reset 2v/div 100s/div zero-current detection waveform max5965a toc17 100ms/div int 2v/div i out_ 200ma/div v gate_ 10v/div 0v 0v 0a v ee v agnd - v out 20v/div overcurrent restart delay max5965a toc18 400ms/div i out_ 200ma/div v gate_ 10v/div 0v 0a v ee v agnd - v out 20v/div startup with valid pd (25k i and 0.1 f) max5965a toc19 i out_ 100ma/div v agnd - v out _ 20v/div v gate_ 5v/div 0v 0a v ee 100s/div detection with invalid pd (25k i and 10 f) max5965a toc20 i out_ 1ma/div 0v 0a v agnd - v out _ 20v/div v gate_ 10v/div v ee 400ms/div detection with invalid pd (15k ? ) max5965a toc21 100ms/div i out_ 1ma/div 0a 0v v agnd - v out 5v/div
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 11 detection with invalid pd (33k ? ) max5965a toc22 100ms/div i out_ 1ma/div 0a 0v v agnd - v out 5v/div startup in midspan mode with valid pd (25k i and 0.1 f) max5965a toc23 i out_ 100ma/div v agnd - v out _ 20v/div v gate_ 5v/div 0v 0a v ee 100ms/div detection with midspan mode with invalid pd (15k ? ) max5965a toc24 400ms/div i out_ 1ma/div 0a 0v v agnd - v out 5v/div v gate_ 10v/div v ee detection with midspan mode with invalid pd (33k ? ) max5965a toc25 400ms/div i out_ 1ma/div 0a 0v v agnd - v out 5v/div v gate_ 10v/div v ee output shorted max5965a toc26 i out_ 1ma/div v agnd - v out _ 5v/div v gate_ 10v/div 0v 0a v ee 40ms/div detection with invalid pd (open circuit, using typical operating circuit 1 ) max5965a toc27 40ms/div i out_ 1ma/div 0a 0v v agnd - v out 5v/div v gate_ 10v/div v ee typical operating characteristics (continued) (v ee = -48v, v dd = +3.3v, v auto = v agnd = v dgnd = 0v, reset = shd_ = unconnected, r sense_ = 0.5 ? , ivee = 00, icut = 000, t a = +25c, all registers = default setting, unless otherwise noted.)
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 12 ______________________________________________________________________________________ detection with invalid pd (open circuit, using typical operating circuit 2 ) max5965a toc28 40ms/div i out_ 1ma/div 0a 0v v agnd - v out 5v/div v gate_ 10v/div v ee startup with different pd classes max5965a toc29 i out_ 20ma/div 0v 0a v agnd - v out _ 5v/div class 1 class 2 class 3 class 4 class 5 40ms/div 2-event classification with a class 4 pd max5965a toc30 i out_ 20ma/div v agnd - v out _ 5v/div v gate_ 10v/div 0v 0a v ee 40ms/div typical operating characteristics (continued) (v ee = -48v, v dd = +3.3v, v auto = v agnd = v dgnd = 0v, reset = shd_ = unconnected, r sense_ = 0.5 ? , ivee = 00, icut = 000, t a = +25c, all registers = default setting, unless otherwise noted.)
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 13 pin description pin name function 1 reset hardware reset. pull reset low for at least 300s to reset the device. all internal registers reset to their default value. the address (a0Ca3), and auto and midspan input-logic levels latch on during low-to- high transition of reset . reset is internally pulled up to v dd with a 50k ? resistor. 2 midspan midspan mode input. an internal 50k ? pulldown resistor to dgnd sets the default mode to endpoint pse operation (power-over-signal pairs). pull midspan to v dig to set midspan operation. the midspan value latches after the device is powered up or reset (see the pd detection section). 3 int open-drain interrupt output. int goes low whenever a fault condition exists. reset the fault condition using software or by pulling reset low (see the interrupt section for more information about interrupt management). 4 scl serial interface clock line input 5 sdaout serial output data line. connect the data line optocoupler input to sdaout (see the typical operating circuits ). connect sdaout to sdain if using a 2-wire, i 2 c-compatible system. pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 osc auto out1 gate1 sense1 out2 gate4 gate2 sense2 v ee out3 gate3 sense3 out4 det4 det3 det2 det1 a0 a1 a2 a3 sdain sdaout scl midspan ssop top view max5965a max5965b 22 21 20 19 15 16 17 18 sense4 agnd v dd dgnd reset int shd1 shd2 shd3 shd4 +
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 14 ______________________________________________________________________________________ pin description (continued) pin name function 6 sdain serial interface input data line. connect the data line optocoupler output to sdain (see the typical operating circuits ). connect sdain to sdaout if using a 2-wire, i 2 c-compatible system. 7C10 a3Ca0 address bits. a3Ca0 form the lower part of the devices address. address inputs default high with an internal 50k ? pullup resistor to v dd . the address values latch when v dd or v ee ramps up and exceeds its uvlo threshold or after a reset. the 3 msbs of the address are set to 010. 11C14 det1Cdet4 detection/classification voltage outputs. use det1 to set the detection and classification probe voltages on port 1. use det1 for the ac voltage sensing of port 1 when using the ac disconnect scheme (see the typical operating circuits ). 15 dgnd digital ground. connect to digital ground. 16 v dd positive digital supply. connect to a digital power supply (reference to dgnd). 17C 20 shd1 C shd4 port shutdown inputs. pull shd_ low to turn off the external fet on port_. internally pulled up to v dd with a 50k ? resistor. 21 agnd analog ground. connect to the high-side analog supply. 22, 25, 29, 32 sense4, sense3, sense2, sense1 mosfet source current-sense negative inputs. connect to the source of the power mosfet and connect a current-sense resistor between sense_ and v ee (see the typical operating circuits ). 23, 26, 30, 33 gate4, gate3, gate2, gate1 port_ mosfet gate drivers. connect gate_ to the gate of the external mosfet (see the typical operating circuits ). 24, 27, 31, 34 out4, out3, out2, out1 mosfet drain-output voltage senses. connect out_ to the power mosfet drain through a resistor (100 ? to 100k ? ). the low leakage at out_ limits the drop across the resistor to less than 100mv (see the typical operating circuits ). 28 v ee low-side analog supply input. connect the low-side analog supply to v ee (-48v). bypass with a 1f capacitor between agnd and v ee . 35 auto auto or shutdown mode input. force auto high to enter auto mode after a reset or power-up. drive low to put the max5965a/max5965b into shutdown mode. in shutdown mode, software controls the operational modes of the max5965a/max5965b. a 50k ? internal pulldown resistor defaults to auto low. auto latches when v dd or v ee ramps up and exceeds its uvlo threshold or when the device resets. software commands can take the max5965a/max5965b out of auto while auto is high. 36 osc oscillator input. ac-disconnect detection function uses osc. connect a 100hz 10%, 2v p-p 5%, +1.3v offset sine wave to osc. if the oscillator positive peak falls below the osc_fail threshold of 2v, the ports that have the ac function enabled shut down and are not allowed to power-up. when not using the ac- disconnect detection function, leave osc unconnected.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 15 functional diagram 50 a 90 a 100ma max fast discharge control 212mv 182mv 13v clamp current-limit detector 4mv overcurrent (ovc) open circuit (oc) current limit (ilim) pwr_en_ 10v voltage sensing foldback control 9-bit adc converter voltage probing and current-limit control current sensing sense_ gate_ out_ det_ a = 3 ac detection* acd_enable ac disconnect signal (acd) acd reference current detection/ classification sm port state machine (sm) register file three-wire serial port interface auto midspan a0 a1 a2 a3 analog bias/ supply monitor agnd *ac detection only for the max5965b. v ee v dd dgnd +10v analog +5v dig voltage references current references central logic unit (clu) dgnd osc scl sdain sdaout v dd oscillator monitor shd_ reset int max5965a/max5965b 9-bit adc register file current measurement
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 16 ______________________________________________________________________________________ detailed description the max5965a/max5965b are quad -48v power con- trollers designed for use in ieee 802.3af-compliant/ieee 802.3at-compatible pse. the devices provide pd discov- ery, classification, current limit, dc and ac load discon- nect detections in compliance with the ieee 802.3af standard. the max5965a/max5965b are pin compatible with the max5952/max5945/ltc4258/ltc4259a pse controllers and provides additional features. the max5965a/max5965b feature a high-power mode, which provides up to 45w per port. the devices allow the user to program the current-limit and overcurrent thresholds up to 2.5 times the default thresholds. the max5965a/max5965b can also be programmed to decrease the current-limit and overcurrent threshold by 15% for high operating voltage conditions to keep the output power constant. the max5965a/max5965b provide new class 5 and 2- event classification (class 6) for detection and classifica- tion of high-power pds. the max5965a/max5965b provide instantaneous readout of each port current through the i 2 c interface. the max5965a/max5965b also provide high-capacitance detection for legacy pds. the max5965a/max5965b are fully software config- urable and programmable through an i 2 c-compatible, 3-wire serial interface with 49 registers. the class-over- current detection function enables system power man- agement to detect if a pd draws more than the allowable current. the max5965a/max5965bs exten- sive programmability enhances system flexibility, enables field diagnosis, and allows for uses in other applications. the max5965a/max5965b provide four operating modes to suit different system requirements. auto mode allows the device to operate automatically without any software supervision. semi-auto mode automatically detects and classifies a device connected to a port after initial software activation but does not power up that port until instructed to by software. manual mode allows total software control of the device and is useful for system diagnostics. shutdown mode terminates all activities and securely turns off power to the ports. the max5965a/max5965b provide input undervoltage lockout, input undervoltage detection, a load-stability safety check during detection, input overvoltage lockout, overtemperature detection, output voltage slew-rate limit during startup, power-good, and fault status. the max5965a/max5965bs programmability includes start- up timeout, overcurrent timeout, and load-disconnect detection timeout. the max5965a/max5965b communicate with the sys- tem microcontroller through an i 2 c-compatible inter- face. the max5965a/max5965b feature separate input and output data lines (sdain and sdaout) for use with optocoupler isolation. as slave devices, the max5965a/max5965b include four address inputs allowing 16 unique addresses. a separate int output and four independent shutdown inputs ( shd_ ) provide fast response from a fault to port shutdown between the max5965a/max5965b and the microcontroller. a reset input allows hardware reset of the device. reset reset is a condition the max5965a/max5965b enter after any of the following conditions: 1) after power-up (v ee and v dd rise above their uvlo thresholds). 2) hardware reset. the reset input is driven low and back high again any time after power-up. 3) software reset. writing a 1 into r1ah[4] any time after power-up. 4) thermal shutdown. during a reset, the max5965a/max5965b reset their register map to the reset state as shown in table 37 and latch in the state of auto (pin 35) and midspan (pin 2). during normal operation, change at the auto and midspan input is ignored. while the condition that caused the reset persists (i.e. high temperature, reset input low, or uvlo conditions) the max5965a/ max5965b do not acknowledge any addressing from the serial interface. port reset (r1ah[3:0]) set high anytime during normal operation to turn off power and clear the events and status registers of the corresponding port. port reset only resets the events and status registers. midspan mode in midspan mode, the device adopts cadence timing during the detection phase. when cadence timing is enabled and a failed detection occurs, the port waits between 2s and 2.4s before attempting to detect again. midspan mode is activated by setting r11h[1] high. the status of the midspan pin is written to r11h[1] during power-up or after a reset. midspan is internally pulled low by a 50k ? resistor.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 17 operation modes the max5965a/max5965b contain four independent, but identical state machines to provide reliable and real- time control of the four network ports. each state machine has four operating modes: auto mode, semi- auto mode, manual, and shutdown. auto mode allows the device to operate automatically without any software supervision. semi-auto mode, upon request, continuous- ly detects and classifies a device connected to a port but does not power up that port until instructed by soft- ware. manual mode allows total software control of the device and is useful in system diagnostics. shutdown mode terminates all activities and securely turns off power to the ports. switching between auto, semi, or manual mode does not interfere with the operation of the port. when the port is set into shutdown mode, all the port operations are immediately stopped and the port remains idle until shutdown is exited. automatic (auto) mode enter automatic (auto) mode by forcing the auto input high prior to a reset, or by setting r12h[p_m1,p_m0] to [1,1] during normal operation (see tables 16a and 16b). in auto mode, the max5965a/max5965b per- forms detection, classification, and power up the port automatically once a valid pd is detected at the port. if a valid pd is not connected at the port, the max5965a/max5965b repeat the detection routine continuously until a valid pd is connected. going into auto mode, the det_en_ and class_en_ bits are set to high and stay high unless changed by software. using software to set det_en_ and/or class_en_ low causes the max5965a/max5965b to skip detection and/or classification. as a protection, dis- abling the detection routine in auto mode does not allow the corresponding port to power up, unless the det_by (r23h[4]) is set to 1. the auto status is latched into the register only dur- ing a reset. any changes to the auto input after reset are ignored. semi-automatic (semi-auto) mode enter semi-auto mode by setting r12h[p_m1,p_m0] to [1,0] during normal operation (see tables 16a and 16b). in semi-auto mode, the max5965a/max5965b, upon request, perform detection and/or classification repeatedly but do not power up the port(s), regardless of the status of the port connection. setting r19h[pwr_on_] (table 22) high immediately terminates detection/classification routines and turns on power to the port(s). r14h[det_en_, class_en_] default to low in semi-auto mode. use software to set r14h[det_en_, class_en_] to high to start the detection and/or classification rou- tines. r14h[det_en_, class_en_] are reset every time the software commands a power off of the port (either through reset or pwr_off_). in any other case, the sta- tus of the bits is left unchanged (including when the state machine turns off the power because a load disconnect or a fault condition is encountered). manual mode enter manual mode by setting r12h[p_m1,p_m0] to [0,1] during normal operation (see tables 16a and 16b). manual mode allows the software to dictate any sequence of operation. write a 1 to both r14h[det_en_] and r14h[class_en_] to start detection and classifica- tion operations, respectively, and in that priority order. after execution, the command is cleared from the regis- ter(s). pwr_on_ has highest priority. setting pwr_on_ high at any time causes the device to immediately enter the powered mode. setting det_en_ and class_en_ high at the same time causes detection to be performed first. once in the powered state, the device ignores det_en_ or class_en_ commands. when switching to manual mode from another mode, det_en_, class_en_ default to low. these bits become pushbutton rather than configuration bits (i.e., writing ones to these bits while in manual mode com- mands the device to execute one cycle of detection and/or classification. the bits are reset back to zero at the end of the execution). shutdown mode enter shutdown mode by forcing the auto input low prior to a reset, or by setting r12h[p_m1,p_m0] to [0,0] during normal operation (see tables 16a and 16b). putting the max5965a/max5965b into shutdown mode immediately turns off power and halts all operations to the corresponding port. the event and status bits of the affected port(s) are also cleared. in shutdown mode, the det_en_, class_en_, and pwr_on_ commands are ignored. in shutdown mode, the serial interface operates normally. pd detection when pd detection is activated, the max5965a/ max5965b probe the output for a valid pd. after each detection cycle, the device sets the det_end_ bit r04h/05h[3:0] high and reports the detection results in the status registers r0ch[2:0], r0dh[2:0], r0eh[2:0], and r0fh[2:0]. the det_end_ bit is reset to low when read through r05h or after a port reset.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 18 ______________________________________________________________________________________ a valid pd has a 25k ? discovery signature characteristic as specified in the ieee 802.3af/at standard. table 1 shows the ieee 802.3af/at specification for a pse detect- ing a valid pd signature. see the typical operating circuits and figure 1a (detection, classification, and power-up port sequence). the max5965a/max5965b can probe and categorize different types of devices con- nected to the port such as: a valid pd, an open circuit, a low resistive load, a high resistive load, a high capacitive load, a positive dc supply, or a negative dc supply. during detection, the max5965a/max5965b keep the external mosfet off and force two probe voltages through the det_ input. the current through the det_ input is measured as well as the voltage at out_. a two-point slope measurement is used as specified by the ieee 802.3af standard to verify the device connect- ed to the port. the max5965a/max5965b implement appropriate settling times and a 100ms digital integra- tion to reject 50hz/60hz power-line noise coupling. an external diode, in series with the det_ input, restricts pd detection to the first quadrant as specified by the ieee 802.3af/at standard. to prevent damage to non-pd devices, and to protect themselves from an output short circuit, the max5965a/max5965b limit the current into det_ to less than 2ma maximum during pd detection. in midspan mode, the max5965a/max5965b wait 2.2s before attempting another detection cycle after every failed detection. the first detection, however, happens immediately after issuing the detection command. high-capacitance detection the clc_en bit in register r23h[5] enables the large capacitor detection feature for legacy pd devices. when clc_en = 1, the high-capacitance detection limit is extended up to 150f. clc_en = 0 is the default condition for the normal capacitor size detection. see table 1 and the register map and description section. table 1. pse pi detection modes electrical requirement (table 33-2 of the ieee 802.3af standard) parameter symbol min max units additional information open-circuit voltage v oc 30 v in detection mode only short-circuit current i sc 5 ma in detection mode only valid test voltage v valid 2.8 10 v voltage difference between test points ? v test 1v time between any two test points t bp 2ms this timing implies a 500hz maximum probing frequency slew rate v slew 0.1 v/s accept signature resistance r good 19 26.5 k ? reject signature resistance r bad < 15 > 33 k ? open-circuit resistance r open 500 k ? accept signature capacitance c good 150 nf reject signature capacitance c bad 10 f signature offset voltage tolerance v os 0 2.0 v signature offset current tolerance i os 012a
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 19 powered device classification (pd classification) during the pd classification mode, the max5965a/ max5965b force a probe voltage (-18v) at det_ and measure the current into det_. the measured current determines the class of the pd. after each classification cycle, the device sets the cl_end_ bit (r04h/05h[7:4]) high and reports the clas- sification results in the status registers r0ch[6:4], r0dh[6:4], r0eh[6:4], and r0fh[6:4]. the cl_end_ bit is reset to low when read through register r05h or after a port reset. both events registers, r04h, and r05h are cleared after the port powers down. table 2 shows the ieee 802.3af requirement for a pse classifying a pd at the power interface (pi). the max5965a/max5965b support high power beyond the ieee 802.3af standard by providing additional clas- sifications (class 5 and 2-event classification). class 5 pd classification during classification, if the max5965a/max5965b detect currents in excess of i class > 48ma, then the pd will be classified as a class 5 powered device. status registers r0ch[6:4] or r0dh[6:4] or r0eh[6:4] or r0fh[6:4] will report the class 5 classification result. 2-event (class 6) pd classification when 2-event classification is activated, the classifica- tion cycle is repeated three times with 8ms wait time between each cycle (see figure 1b). between each classification cycle, the max5965a/max5965b do not reset the port voltage completely but keeps the output voltage at -9v. the en_cl6 bits in r1ch[7:4] enable 2- event classification on a per port basis. powered state when the max5965a/max5965b enter a powered state, the t start and t disc timers are reset. before turning on the port power, the max5965a/max5965b check if any other port is not turning on and if the t fault timer is zero. another check is performed if the acd_en_ bit is set, in this case the osc_fail bit must be low (oscillator is okay) for the port to be powered. if these conditions are met, the max5965a/max5965b enter startup where it turns on power to the port. an internal signal, pok_, asserts high when v out_ is within 2v from v ee . pgood_ status bits are set high if pok_ stays high longer than t pgood . pgood_ immediately resets when pok_ goes low (see figure 2). the pg_chg_ bit sets when a port powers up or down. pwr_en_ sets when a port powers up and resets when a port shuts down. the port shutdown timer lasts 0.5ms and prevents other ports from turning off during that peri- od, except in the case of emergency shutdowns ( reset = l, reset_ic = h, v eeuvlo, v dduvlo, and t shd ). the max5965a/max5965b always check the status of all ports before turning off. a priority logic system deter- mines the order to prevent the simultaneous turn-on or turn-off of the ports. the port with the lesser ordinal number gets priority over the others (i.e., port 1 turns on first, port 2 second, port 3 third, and port 4 fourth). setting pwr_off_ high turns off power to the corre- sponding port. table 2. pse classification of a pd (refer to table 33-4 of the ieee 802.3af) measured i class (ma) classification 0 to 5 class 0 > 5 and < 8 may be class 0 and 1 8 to 13 class 1 > 13 and < 16 may be class 1 or 2 16 to 21 class 2 > 21 and < 25 may be class 2 or 3 25 to 31 class 3 > 31 and < 35 may be class 3 or 4 35 to 45 class 4 > 45 and < 51 may be class 4 or 5 51 to 68 class 5
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 20 ______________________________________________________________________________________ figure 1a. detection, classification, and power-up port sequence out_ -4v -9v -18v -48v t t deti t detii t class 150ms 150ms 21.3ms 0v 0v 80ms figure 1b. detection, 2-event classification, and power-up port sequence 150ms 150ms 21.3ms t classi t deti t detii t classii 8ms 8ms t classiii 21.3ms 21.3ms 80ms 0 t 0v -4v -9v out_ -18v -48v
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 21 overcurrent protection a sense resistor r s connected between sense_ and v ee monitors the load current. under normal operating conditions, the voltage across r s (v rs ) never exceeds the threshold v su_lim . if v rs exceeds v su_lim , an internal current-limiting circuit regulates the gate_ volt- age, limiting the current to i lim = v su_lim /r s . during transient conditions, if v rs exceeds v su_lim by more than 1v, a fast pulldown circuit activates to quickly recover from the current overshoot. during startup, if the current-limit condition persists, when the startup timer, t start , times out, the port shuts off, and the strt_flt_ bit is set. in the normal powered state, the max5965a/max5965b check for overcurrent condi- tions as determined by v flt_lim = ~88% of v su_lim . the t fault counter sets the maximum allowed continu- ous overcurrent period. the t fault counter increases when v rs exceeds v flt_lim and decreases at a slower pace when v rs drops below v flt_lim . a slower decre- ment for the t fault counter allows for detecting repeat- ed short-duration overcurrents. when the counter reaches the t fault limit, the max5965a/max5965b power off the port and assert the imax_flt_ bit. for a continuous overstress, a fault latches exactly after a period of t fault . v su_lim is programmable through the icut registers r2ah[6:4], r2ah[2:0], r2bh[6:4], r2bh[2:0], and the ivee bits in register r29h[1:0]. see the high-power mode section for more information on the icut register. after power-off due to an overcurrent fault, and if the rstr_en bit is set, the t fault timer is not immediately reset but starts decrementing at the same slower pace. the max5965a/max5965b allow the port to be pow- ered on only when the t fault counter is at zero. this feature sets an automatic duty-cycle protection to the external mosfet avoiding overheating. the max5965a/max5965b continuously flag when the current exceeds the maximum current allowed for the class as indicated in the class status register. when class overcurrent occurs, the max5965a/max5965b set the ivc_ bit in register r09h. icut register and high-power mode icut register the icut register determines the maximum current lim- its allowed for each port of the max5965a/max5965b. the 3 icut bits (r2ah[6:4], r2ah[2:0], r2bh[6:4], and r2bh[2:0]) allow programming of the current-limit and overcurrent thresholds in excess of the ieee standard limit (see tables 34a, 34b, and 34c). the icut regis- ters can be written to directly through the i 2 c interface when cl_disc (r17h[2]) is set to 0 (see table 3). in this case, the current limit of the port is configured regardless of the status of the classification. by setting the cl_disc bit to 1, the max5965a/ max5965b automatically set the icut register based upon the classification result of the port. see table 3 and the register map and description section. high-power mode when cl_disc (r17h[2]) is set to 0, high-power mode is configured by setting the icut bits to any combina- tion other than 000, 110, or 111 (note that 000 is the default value for the ieee standard limit). see table 3 and the register map and description section. foldback current during startup and normal operation, an internal circuit senses the voltage at out_ and reduces the current- limit value when (v out _ - v ee ) > 28v. the foldback function helps to reduce the power dissipation on the fet. the current limit eventually reduces down to 1/3 of i lim when (v out _ - v ee ) > 48v (see figure 3a). for high-power mode, the foldback starts when (v out _ - v ee ) > 10v (see figure 3b). in high-power mode, the current limit (i lim ) is reduced down to minimum fold- back current (v th_fb /r s ) when (v out _ - v ee ) > 48v. figure 2. pgood_ timing pgood_ pok_ t pgood
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 22 ______________________________________________________________________________________ table 3. automatic icut programming cl_disc port classification result enx_cl6 en_hp_all en_hp_cl6 en_hp_cl5 en_hp_cl4 resulting icut register bits 0 any x x x x x user programmed 1 1 x x x x x icut = 110 1 2 x x x x x icut = 111 1 0, 3 x x x x x icut = 000 1 4, 5 x 0 x x x icut = 000 1 5 x 1 x 1 x icut = r24h[6:4] 1 5 x 1 x 0 x icut = 000 1 4 x 1 x x 1 icut = r24h[6:4] 1 4 x 1 x x 0 icut = 000 1 6 or illegal 0 x x x x 1 6 or illegal 1 1 1 x x (see table 35a) 1 6 or illegal 1 1 0 x x icut = 000 1 6 or illegal 1 0 x x x icut = 000 mosfet gate driver connect the gate of the external n-channel mosfet to gate_. an internal 50a current source pulls gate_ to (v ee + 10v) to turn on the mosfet. an internal 40a current source pulls down gate_ to v ee to turn off the mosfet. the pullup and pulldown current controls the maximum slew rate at the output during turn-on or turn-off. use the following equation to set the maximum slew rate: where c gd is the total capacitance between gate and drain of the external mosfet. current limit and the capacitive load at the drain control the slew rate during startup. during current-limit regulation, the max5965a/max5965b manipulate the gate_ voltage to control the voltage at sense_ (v rs ). a fast pulldown activates if v rs overshoots the limit threshold (v su_lim ). the fast pulldown current increases with the amount of overshoot. the maximum fast pulldown cur- rent is 100ma. during turn-off, when the gate_ voltage reaches a value lower than 1.2v, a strong pulldown switch is acti- vated to keep the mosfet securely off. ? ? v t i c out gate gd = figure 3a. foldback current characteristics 48v 28v v su_lim v su_lim / 3 (v rs - v ee ) (v out_ - v ee ) figure 3b. foldback current characteristics for high-power mode 48v 10v v su_lim v th_fb (v rs - v ee ) (v out_ - v ee )
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 23 digital logic v dd supplies power for the internal logic circuitry. v dd ranges from +3.0v to +5.5v and determines the logic thresholds for the cmos connections (sdain, sdaout, scl, auto, shd_ , a_). this voltage range enables the max5965a/max5965b to interface with a nonisolated low-voltage microcontroller. the max5965a/max5965b check the digital supply for compatibility with the internal logic. the max5965a/max5965b also feature a v dd undervoltage lockout (v dduvlo ) of +2.0v. a v dduvlo condition keeps the max5965a/max5965b in reset and the ports shut off. bit 0 in the supply event register shows the status of v dduvlo (table 12) after v dd has recov- ered. all logic inputs and outputs reference to dgnd. for ac-disconnected detection, dgnd and agnd must be connected together externally. connect dgnd to agnd at a single point in the system as close as possi- ble to the max5965a/max5965b. hardware shutdown shd_ shuts down the respective ports without using the serial interface. hardware shutdown offers an emer- gency turn-off feature that allows a fast disconnect of the power supply from the port. pull shd_ low to remove power. shd_ also resets the corresponding events and status register bits. interrupt the max5965a/max5965b contain an open-drain logic output ( int ) that goes low when an interrupt condition exists. r00h and r01h (tables 6 and 7) contain the defin- itions of the interrupt registers. the mask register r01h determines events that trigger an interrupt. as a response to an interrupt, the controller reads the status of the event register to determine the cause of the interrupt and takes subsequent actions. each interrupt event register also contains a clear on read (cor) register. reading through the cor register address clears the interrupt. int remains low when reading the interrupt through the read- only addresses. for example, to clear a startup fault on the port 4 read address 09h (see table 11). use the glob- al pushbutton bit in register 1ah (bit 7, table 23) to clear interrupts, or use a software or hardware reset. undervoltage and overvoltage protection the max5965a/max5965b contain several undervoltage and overvoltage protection features. table 12 in the register map and description section shows a detailed list of the undervoltage and overvoltage protection fea- tures. an internal v ee undervoltage lockout (v eeuvlo ) cir- cuit keeps the mosfet off and the max5965a/ max5965b in reset until v agnd - v ee exceeds 29v for more than 3ms. an internal v ee overvoltage (v ee_ov ) cir- cuit shuts down the ports when (v agnd - v ee ) exceeds 60v. the digital supply also contains an undervoltage lockout (v dduvlo ). the max5965a/max5965b also fea- ture three other undervoltage and overvoltage interrupts: v ee undervoltage interrupt (v ee_uv ), v dd undervoltage interrupt (v dd_uv ), and v dd overvoltage interrupt (v dd_ov ). a fault latches into the supply events register (table 12), but the max5965a/max5965b does not shut down the ports with v ee_uv , v dd_uv , or v dd_ov . dc disconnect monitoring setting r13h[dcd_en_] bits high enables dc load moni- toring during a normal powered state. if v rs (the voltage across r s ) falls below the dc load disconnect threshold, v dcth , for more than t disc , the device turns off power and asserts the ld_disc_ bit of the corresponding port. ac disconnect monitoring features (max5965b) the max5965b features ac load disconnect monitor- ing. connect an external sine wave to osc. the oscilla- tor requirements are: 1) v p-p x frequency = 200v p-p x hz 15% 2) positive peak voltage > +2.2v 3) frequency > 60hz a 100hz 10%, 2v p-p 5%, with +1.3v offset (v peak = +2.3v typical) is recommended. the max5965b buffers and amplifiers three times the external oscillator signal and sends the signal to det_, where the sine wave is ac-coupled to the output. the max5965b senses the presence of the load by monitor- ing the amplitude of the ac current returned to det_ (see the functional diagram ). setting r13h[acd_en_] bits high enable ac load dis- connect monitoring during a normal powered state. if the ac current peak at the det_ input falls below i acth for more than t disc , the device turns off power and asserts the ld_disc_ bit of the corresponding port. i acth is programmable using r23h[2:0]. an internal comparator checks for a proper amplitude of the oscillator input. if the positive peak of the input sinu- soid falls below a safety value of 2v (typ), osc_fail sets and the port shuts down. power cannot be applied to the ports when acd_en_ is set high and osc_fail is set high. leave osc unconnected or connect it to dgnd when not using ac-disconnect detection. thermal shutdown if the max5965a/max5965b die temperature reaches +150c, an overtemperature fault generates and the max5965a/max5965b shut down. the mosfets turn off. the die temperature of the max5965a/max5965b must cool down below +130c to remove the overtemperature fault condition. after a thermal shutdown, the part is reset.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 24 ______________________________________________________________________________________ watchdog the r1eh and r1fh registers control the watchdog operation. the watchdog function, when enabled, allows the max5965a/max5965b to gracefully take over con- trol or securely shuts down the power to the ports in case of software/firmware crashes. contact the factory for more details. address inputs a3, a2, a1, and a0 represent the 4 lsbs of the chip address. the complete chip address is 7 bits (see table 4). the 4 lsbs latch on the low-to-high transition of reset or after a power-supply start (either on v dd or v ee ). address inputs default high through an internal 50k ? pullup resistor to v dd . the max5965a/max5965b also respond to the call through a global address 30h (see the global addressing and alert response protocol section). i 2 c-compatible serial interface the max5965a/max5965b operate as a slave that sends and receives data through an i 2 c-compatible, 2- wire or 3-wire interface. the interface uses a serial-data input line (sdain), a serial-data output line (sdaout), and a serial-clock line (scl) to achieve bidirectional communication between master(s) and slave(s). a mas- ter (typically a microcontroller) initiates all data transfers to and from the max5965a/max5965b, and generates the scl clock that synchronizes the data transfer. in most applications, connect the sdain and the sdaout lines together to form the serial-data line (sda). using the separate input and output data lines allows optocoupling with the controller bus when an isolated supply powers the microcontroller. the max5965a/max5965b sdain line operates as an input. the max5965a/max5965b sdaout operates as an open-drain output. a pullup resistor, typically 4.7k ? , is required on sdaout. the max5965a/max5965b scl line operates only as an input. a pullup resistor, typically 4.7k ? , is required on scl if there are multiple masters, or if the master in a single-master system has an open- drain scl output. 0 1 0 a3 a2 a1 a0 r/ w table 4. max5965a/max5965b address figure 4. 2-wire, serial-interface timing details scl sdain t low t high t r t f t buf start condition stop condition repeated start condition start condition t hd, sta t su, dat t hd, dat t su, sta t hd, sta t su, sto figure 5. 3-wire, serial-interface timing details scl sdain/sda t low t high t r t f t buf start condition stop condition repeated start condition start condition t hd, sta t su, dat t hd, dat t su, sta t hd, sta t su, sto
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 25 serial addressing each transmission consists of a start condition (figure 6) sent by a master, followed by the max5965a/ max5965b 7-bit slave address plus r/ w bit, a register address byte, one or more data bytes, and finally a stop condition. start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmis- sion with a start (s) condition by transitioning sda from high to low while scl is high. when the master fin- ishes communicating with the slave, the master issues a stop (p) condition by transitioning sda from low to high while scl is high. the stop condition frees the bus for another transmission. bit transfer each clock pulse transfers one data bit (figure 7). the data on sda must remain stable while scl is high. acknowledge the acknowledge bit is a clocked 9th bit (figure 8) that the recipient uses to handshake receipt of each byte of data. thus each byte effectively transferred requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda (or the sdaout in the 3-wire interface) during the acknowledge clock pulse, so that the sda line is stable low during the high period of the clock pulse. when the master transmits to the max5965a/max5965b, the max5965a/max5965b generate the acknowledge bit. when the max5965a/ max5965b transmit to the master, the master gener- ates the acknowledge bit. figure 6. start and stop conditions start stop sp sda/ sdain scl figure 7. bit transfer sda scl data line stable; data valid . change of data allowed figure 8. acknowledge scl sda by transmitter clock pulse for acknowledgement start condition sda by receiver 12 89 s
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 26 ______________________________________________________________________________________ figure 9. slave address sdain/sda scl 1 0 a3 a2 a1 a0 0 msb lsb ack r/w figure 10. control byte received saap 0 slave address control byte acknowledge from the max5965a/max5965b acknowledge from the max5965a/max5965b d15 d14 d13 d12 d11 d10 d9 d8 control byte is stored on receipt of stop condition r/w slave address the max5965a/max5965b have a 7-bit long slave address (figure 9). the bit following the 7-bit slave address (bit eight) is the r/ w bit, which is low for a write command and high for a read command. 010 always represents the first 3 bits (msbs) of the max5965a/max5965b slave address. slave address bits a3, a2, a1, and a0 represent the states of the max5965a/max5965bs a3, a2, a1, and a0 inputs, allowing up to sixteen max5965a/max5965b devices to share the bus. the states of the a3, a2, a1, and a0 latch in upon the reset of the max5965a/max5965b into register r11h. the max5965a/max5965b monitor the bus continuously, waiting for a start condition fol- lowed by the max5965a/max5965bs slave address. when a max5965a/max5965b recognizes its slave address, the max5965a/max5965b acknowledge and are then ready for continued communication. global addressing and alert response protocol the global address call is used in writing mode to write the same register to multiple devices (address 0x60). in read mode (address 0x61), the global address call is used as the alert response address. when responding to a global call, the max5965a/max5965b put their own address out on the data line whenever the interrupt is active. every other device connected to the sdaout line that has an active interrupt also does this. after every bit transmitted, the max5965a/max5965b check that the data line effectively corresponds to the data it is delivering. if it is not, it then backs off and frees the data line. this litigation protocol always allows the part with the lowest address to complete the transmission. the microcontroller can then respond to the interrupt and take proper actions. the max5965a/max5965b do not reset their own interrupt at the end of the alert response protocol. the microcontroller has to do it by clearing the event register through their cor adresses or activating the clr_int pushbutton. message format for writing to the max5965a/max5965b a write to the max5965a/max5965b comprises of the max5965a/max5965bs slave address transmission with the r/ w bit set to 0, followed by at least 1 byte of information. the first byte of information is the com- mand byte (figure 10). the command byte determines which register of the max5965a/max5965b is written to by the next byte, if received. if the max5965a/ max5965b detect a stop condition after receiving the command byte, the max5965a/max5965b take no fur- ther action beyond storing the command byte. any bytes received after the command byte are data bytes. the first data byte goes into the internal register of the max5965a/max5965b selected by the command byte. if the max5965a/max5965b transmit multiple data bytes before the max5965a/max5965b detect a stop condition, these bytes store in subsequent max5965a/ max5965b internal registers because the control byte address autoincrements.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 27 message format for reading the max5965a/max5965b read using the max5965a/ max5965bs internally stored command byte as an address pointer, the same way the stored command byte is used as an address pointer for a write. the point- er autoincrements after reading each data byte using the same rules as for a write. thus, a read is initiated by first configuring the max5965a/max5965bs command byte by performing a write. the master now reads n consec- utive bytes from the max5965a/max5965b, with the first data byte read from the register addressed by the initial- ized command byte. when performing read-after-write verification, remember to reset the command bytes address because the stored control byte address autoin- crements after the write. operation with multiple masters when the max5965a/max5965b operate on a 2-wire interface with multiple masters, a master reading the max5965a/max5965b should use repeated starts between the write which sets the max5965a/ max5965bs address pointer, and the read(s) that take the data from the location(s). it is possible for master 2 to take over the bus after master 1 has set up the max5965a/max5965bs address pointer but before mas- ter 1 has read the data. if master 2 subsequently resets the max5965a/max5965bs address pointer then master 1s read may be from an unexpected location. command address autoincrementing address autoincrementing allows the max5965a/ max5965b to be configured with fewer transmissions by minimizing the number of times the command address needs to be sent. the command address stored in the max5965a/max5965b generally incre- ments after each data byte is written or read (table 5). the max5965a/max5965b are designed to prevent overwrites on unavailable register addresses and unin- tentional wrap-around of addresses. figure 11. control and single data byte received saaap 0 slave address control byte data byte acknowledge from the max5965a/max5965b 1 byte autoincrement memory word address d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 how control byte and data byte map into the register acknowledge from the max5965a/max5965b acknowledge from the max5965a/max5965b r/w figure 12. n data bytes received saaap 0 slave address control byte data byte acknowledge from the max5965a/max5965b n bytes autoincrement memory word address d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 how control byte and data byte map into the register acknowledge from the max5965a/max5965b acknowledge from the max5965a/max5965b r/w table 5. autoincrement rules command byte address range autoincrement behavior 0x00 to 0x26 command address autoincrements after byte read or written 0x26 command address remains at 0x26 after byte written or read
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 28 ______________________________________________________________________________________ table 6. interrupt register address = 00h symbol bit r/w description sup_flt 7 r interrupt signal for supply faults. sup_flt is the logic or of all the bits [7:0] in register r0ah/r0bh (table 12). tstr_flt 6 r interrupt signal for startup failures. tstr_flt is the logic or of bits [7:0] in register r08h/r09h (table 11). imax_flt 5 r interrupt signal for current-limit violations. imax_flt is the logic or of bits [3:0] in register r06h/r07h (table 10). cl_end 4 r interrupt signal for completion of classification. cl_end is the logic or of bits [7:4] in register r04h/r05h (table 9). det_end 3 r interrupt signal for completion of detection. det_end is the logic or of bits [3:0] in register r04h/r05h (table 9). ld_disc 2 r interrupt signal for load disconnection. ld_disc is the logic or of bits [7:4] in register r06h/r07h (table 10). pg_int 1 r interrupt signal for pgood status change. pg_int is the logic or of bits [7:4] in register r02h/r03h (table 8). pen_int 0 r interrupt signal for power-enable status change. pen_int is the logic or of bits [3:0] in register r02h/r03h (table 8). table 7. interrupt mask register address = 01h symbol bit r/w description mask7 7 r/w interrupt mask bit 7. a logic-high enables the sup_flt interrupts. a logic-low disables the sup_flt interrupts. mask6 6 r/w interrupt mask bit 6. a logic-high enables the tstr_flt interrupts. a logic-low disables the tstr_flt interrupts. mask5 5 r/w interrupt mask bit 5. a logic-high enables the imax_flt interrupts. a logic-low disables the imax_flt interrupts. mask4 4 r/w interrupt mask bit 4. a logic-high enables the cl_end interrupts. a logic-low disables the cl_end interrupts. mask3 3 r/w interrupt mask bit 3. a logic-high enables the det_end interrupts. a logic-low disables the det_end interrupts. mask2 2 r/w interrupt mask bit 2. a logic-high enables the ld_disc interrupts. a logic-low disables the ld_disc interrupts. mask1 1 r/w interrupt mask bit 1. a logic-high enables the pg_int interrupts. a logic-low disables the pg_int interrupts. mask0 0 r/w interrupt mask bit 0. a logic-high enables the pen_int interrupts. a logic-low disables the pen_int interrupts. register map and description the interrupt register (table 6) summarizes the event register status and is used to send an interrupt signal ( int goes low) to the controller. writing a 1 to r1ah[7] clears all interrupt and events registers. a reset sets r00h to 00h. int_en (r17h[7]) is a global interrupt mask (table 7). the mask_ bits activate the corresponding interrupt bits in register r00h. writing a 0 to int_en (r17h[7]) disables the int output. a reset sets r01h to aaa00a00b where a is the state of the auto input prior to the reset.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 29 the power event register (table 8) records changes in the power status of the four ports. any change in pgood_ (r10h[7:4]) sets pg_chg_ to 1. any change in the pwr_en_ (r10h[3:0]) sets pwen_chg_ to 1. pg_chg_ and pwen_chg_ trigger on the edges of pgood_ and pwr_en_ and do not depend on the actual level of the bits. the power event register has two addresses. when read through the r02h address, the content of the register is left unchanged. when read through the cor r03h address, the register content is cleared. a reset sets r02h/r03h = 00h. table 8. power event register address 02h 03h symbol bit r/w r/w description pg_chg4 7 r cor pgood change event for port 4 pg_chg3 6 r cor pgood change event for port 3 pg_chg2 5 r cor pgood change event for port 2 pg_chg1 4 r cor pgood change event for port 1 pwen_chg4 3 r cor power enable change event for port 4 pwen_chg3 2 r cor power enable change event for port 3 pwen_chg2 1 r cor power enable change event for port 2 pwen_chg1 0 r cor power enable change event for port 1 table 9. detect event register address 04h 05h symbol bit r/w r/w description cl_end4 7 r cor classification completed on port 4 cl_end3 6 r cor classification completed on port 3 cl_end2 5 r cor classification completed on port 2 cl_end1 4 r cor classification completed on port 1 det_end4 3 r cor detection completed on port 4 det_end3 2 r cor detection completed on port 3 det_end2 1 r cor detection completed on port 2 det_end1 0 r cor detection completed on port 1 det_end_/cl_end_ is set high whenever detection/ classification is completed on the corresponding port. a 1 in any of the cl_end_ bits forces r00h[4] to 1. a 1 in any of the det_end_ bits forces r00h[3] to 1. as with any of the other events register, the detect event register has two addresses. when read through the r04h address, the content of the register is left unchanged. when read through the cor r05h address, the register content is cleared. a reset sets r04h/r05h = 00h.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 30 ______________________________________________________________________________________ if the port remains in current limit or the pgood condi- tion is not met at the end of the startup period, the port shuts down and the corresponding strt_flt_ is set to 1. a 1 in any of the strt_flt_ bits forces r00h[6] to 1. ivc_ is set to 1 whenever the port current exceeds the maximum allowed limit for the class (determined during the classification process). a 1 in any of ivc_ forces r00h[6] to 1. when the cl_disc (r17h[2]) is set to 1, the port also limits the load current according to its class as specified in the electrical characteristics table. as with any of the other events register, the startup event register has two addresses. when read through the r08h address, the content of the register is left unchanged. when read through the cor r09h address, the register content is cleared. a reset sets r08h/r09h = 00h. table 10. fault event register address 06h 07h symbol bit r/w r/w description ld_disc4 7 r cor disconnect on port 4 ld_disc3 6 r cor disconnect on port 3 ld_disc2 5 r cor disconnect on port 2 ld_disc1 4 r cor disconnect on port 1 imax_flt4 3 r cor overcurrent on port 4 imax_flt3 2 r cor overcurrent on port 3 imax_flt2 1 r cor overcurrent on port 2 imax_flt1 0 r cor overcurrent on port 1 table 11. startup event register address 08h 09h symbol bit r/w r/w description ivc4 7 r cor class overcurrent flag for port 4 ivc3 6 r cor class overcurrent flag for port 3 ivc2 5 r cor class overcurrent flag for port 2 ivc1 4 r cor class overcurrent flag for port 1 strt_flt4 3 r cor startup failed on port 4 strt_flt3 2 r cor startup failed on port 3 strt_flt2 1 r cor startup failed on port 2 strt_flt1 0 r cor startup failed on port 1 ld_disc_ is set high whenever the corresponding port shuts down due to detection of load removal. imax_flt_ is set high when the port shuts down due to an extended overcurrent event after a successful start- up. a 1 in any of the ld_disc_ bits forces r00h[2] to 1. a 1 in any of the imax_flt_ bits forces r00h[5] to 1. as with any of the other events register, the fault event register has two addresses. when read through the r06h address, the content of the register is left unchanged. when read through the cor r07h address, the register content is cleared. a reset sets r06h/r07h = 00h.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 31 the max5965a/max5965b continuously monitor the power supplies and set the appropriate bits in the sup- ply event register (table 12). v dd_ov /v ee_ov is set to 1 whenever v dd /v ee exceeds its overvoltage threshold. v dd_uv /v ee_uv is set to 1 whenever v dd /v ee falls below its undervoltage threshold. osc_fail is set to 1 whenever the amplitude of the oscillator signal at the osc input falls below a level that might compromise the ac disconnect detection func- tion. osc_fail generates an interrupt only if at least one of the acd_en (r13h[7:4]) bits is set high. a thermal shutdown circuit monitors the temperature of the die and resets the max5965a/max5965b if the temperature exceeds +150c. tsd is set to 1 after the max5965a/max5965b return to normal operation. tsd is also set to 1 after every uvlo reset. when v dd and/or |v ee | is below its uvlo threshold, the max5965a/max5965b are in reset mode and securely holds all ports off. when v dd and |v ee | rise to above their respective uvlo thresholds, the device comes out of reset as soon as the last supply crosses the uvlo threshold. the last supply corresponding uv and uvlo bits in the supply event register is set to 1. a 1 in any supply event registers bits forces r00h[7] to 1. as with any of the other events register, the supply event register has two addresses. when read through the r0ah address, the content of the register is left unchanged. when read through the cor r0bh address, the register content is cleared. a reset sets r0ah/r0bh to 00100001b if v dd comes up after v ee or to 00010100b if v ee comes up after v dd . table 12. supply event register address 0ah 0bh symbol bit r/w r/w description tsd 7 r cor overtemperature shutdown v dd_ov 6 r cor v dd overvoltage condition v dd_uv 5 r cor v dd undervoltage condition v ee_uvlo 4 r cor v ee undervoltage lockout condition v ee_ov 3 r cor v ee overvoltage condition v ee_uv 2 r cor v ee undervoltage condition osc_fail 1 r cor oscillator amplitude is below limit v dd_uvlo 0 r cor v dd undervoltage lockout condition
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 32 ______________________________________________________________________________________ table 13a. port status registers address = 0ch, 0dh, 0eh, 0fh symbol bit r/w description reserved 7 r reserved 6 r class_[2] 5 r class_[1] class_ 4 r class_[0] reserved 3 r reserved 2 r det_st_[2] 1 r det_st_[1] det_st_ 0 r det_st_[0] table 13b. detection result decoding chart det_st_[2:0] (address = 0ch, 0dh, 0eh, 0fh) detected description 000 none detection status unknown 001 dcp positive dc supply connected at the port (v agnd - v out_ < 1v) 010 high cap high capacitance at the port (> 8.5f) 011 rlow low resistance at the port, r pd < 15k ? 100 det_ok detection pass, 15k ? < r pd < 33k ? 101 rhigh high resistance at the port, r pd > 33k ? 110 open0 open port (i < 10a) 111 dcn negative dc supply connected to the port (v out_ - v ee < 2v) table 13c. classification result decoding chart class_[2:0] (address = 0ch, 0dh, 0eh, 0fh) class result 000 unknown 001 1 010 2 011 3 100 4 101 5 110 0 111 current limit (> i cilim ) the port status register (table 13a) records the results of the detection and classification at the end of each phase in three encoding bits each. r0ch contains the detection and classification status of port 1. r0dh corresponds to port 2, r0eh corresponds to port 3, and r0fh corresponds to port 4. tables 13b and 13c show the detection/classifi- cation result decoding charts, respectively. for clc_en = 0, the detection result is shown in table 13b. when clc_en is set high, the max5965a/max5965b allow valid detection of high capacitive load of up to 150f. when 2-event classification is not enabled (enx_cl6 = 0), the classification status is reported in table 13c. when 2-event classification is enabled (enx_cl6 = 1), the class_[2:0] bits are set to 000 and the classifica- tion result is reported in locations r2chCr2fh. as a protection, when poff_cl (r17h[3], table 21) is set to 1, the max5965a/max5965b prohibit turning on power to the port that returns a status 111 after classifi- cation. a reset sets 0ch, 0dh, 0eh, and 0fh = 00h.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 33 pgood_ is set to 1 (table 14) at the end of the power- up startup period if the power-good condition is met (0 < (v out_ - v ee )< pg th ). the power-good condition must remain valid for more than t pgood to assert pgood_. pgood_ is reset to 0 whenever the output falls out of the power-good condition. a fault condition immediately forces pgood_ low. pwr_en_ is set to 1 when the port power is turned on. pwr_en_ resets to 0 as soon as the port turns off. any transition of pgood_ and pwr_en_ bits set the corre- sponding bit in the power event registers r02h/r03h (table 8). a reset sets r10h = 00h. table 14. power status register address = 10h symbol bit r/w description pgood4 7 r power-good condition on port 4 pgood3 6 r power-good condition on port 3 pgood2 5 r power-good condition on port 2 pgood1 4 r power-good condition on port 1 pwr_en4 3 r power is enabled on port 4 pwr_en3 2 r power is enabled on port 3 pwr_en2 1 r power is enabled on port 2 pwr_en1 0 r power is enabled on port 1 table 15. address input status register address = 11h symbol bit r/w description reserved 7 r reserved reserved 6 r reserved a3 5 r device address, a3 pin latched-in status a2 4 r device address, a2 pin latched-in status a1 3 r device address, a1 pin latched-in status a0 2 r device address, a0 pin latched-in status midspan 1 r midspan inputs latched-in status auto 0 r auto inputs latched-in status a3, a2, a1, a0 (table 15) represent the 4 lsbs of the max5965a/max5965b address (table 4). during a reset, the device latches into r11h. these 4 bits address from the corresponding inputs as well as the state of the midspan and auto inputs. changes to those inputs during normal operation are ignored.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 34 ______________________________________________________________________________________ setting dcd_en_ to 1 enables the dc load disconnect detection feature (table 17). setting acd_en_ to 1 enables the ac load disconnect feature. if enabled, the load disconnect detection starts during power mode and after startup when the corresponding pgood_ bit in register r10h (table 14) goes high. a reset sets r13h = 0000aaaab where a represents the latched-in state of the auto input prior to the reset. table 16a. operating mode register address = 12h symbol bit r/w description p4_m1 7 r/w mode[1] for port 4 p4_m0 6 r/w mode[0] for port 4 p3_m1 5 r/w mode[1] for port 3 p3_m0 4 r/w mode[0] for port 3 p2_m1 3 r/w mode[1] for port 2 p2_m0 2 r/w mode[0] for port 2 p1_m1 1 r/w mode[1] for port 1 p1_m0 0 r/w mode[0] for port 1 table 17. load disconnect detection enable register address = 13h symbol bit r/w description acd_en4 7 r/w enable ac disconnect detection on port 4 acd_en3 6 r/w enable ac disconnect detection on port 3 acd_en2 5 r/w enable ac disconnect detection on port 2 acd_en1 4 r/w enable ac disconnect detection on port 1 dcd_en4 3 r/w enable dc disconnect detection on port 4 dcd_en3 2 r/w enable dc disconnect detection on port 3 dcd_en2 1 r/w enable dc disconnect detection on port 2 dcd_en1 0 r/w enable dc disconnect detection on port 1 table 16b. operating mode status mode description 00 shutdown 01 manual 10 semi-auto 11 auto the max5965a/max5965b use 2 bits for each port to set the mode of operation. set the modes according to table 16a and 16b. a reset sets r12h = aaaaaaaab where a represents the latched-in state of the auto input prior to the reset. use software to change the mode of operation. software resets of ports (reset_p_ bit, table 23) do not affect the mode register.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 35 setting det_en_/class_en_ to 1 (table 18) enables load detection/classification, respectively. detection always has priority over classification. to perform clas- sification without detection, set the det_en_ bit low and class_en_ bit high. in manual mode, r14h works like a pushbutton. set the bits high to begin the corresponding routine. the bit clears after the routine finishes. when entering auto mode, r14h defaults to ffh. when entering semi or manual modes, r14h defaults to 00h. a reset or power-up sets r14h = aaaaaaaab where a represents the latched-in state of the auto input prior to the reset. table 18. detection and classification enable register address = 14h symbol bit r/w description class_en4 7 r/w enable classification on port 4 class_en3 6 r/w enable classification on port 3 class_en2 5 r/w enable classification on port 2 class_en1 4 r/w enable classification on port 1 det_en4 3 r/w enable detection on port 4 det_en3 2 r/w enable detection on port 3 det_en2 1 r/w enable detection on port 2 det_en1 0 r/w enable detection on port 1 table 19. backoff and high-power enable register address = 15h symbol bit r/w description en_hp_all 7 r/w high-power detection enabled en_hp_cl6 6 r/w class 6 pd high-power enabled en_hp_cl5 5 r/w class 5 pd high-power enabled en_hp_cl4 4 r/w class 4 pd high-power enabled bckoff4 3 r/w enable cadence timing on port 4 bckoff3 2 r/w enable cadence timing on port 3 bckoff2 1 r/w enable cadence timing on port 2 bckoff1 0 r/w enable cadence timing on port 1 en_hp_cl_, en_hp_all together with cl_disc (r17h[2]) and enx_cl6 (r1ch[7:4]) are used to program the high-power mode. see table 3 for details. setting bckoff_ to 1 (table 19) enables cadence tim- ing on each port where the port backs off and waits 2.2s after each failed load discovery detection. the ieee 802.3af standard requires a pse that delivers power through the spare pairs (midspan pse) to have cadence timing. a reset or power-up sets r15h = 0000xxxxb where x is the logic and of the midspan and auto inputs.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 36 ______________________________________________________________________________________ table 20a. timing configuration register address = 16h symbol bit r/w description rstr[1] 7 r/w restart timer programming bit 1 rstr[0] 6 r/w restart timer programming bit 0 tstart[1] 5 r/w startup timer programming bit 1 tstart[0] 4 r/w startup timer programming bit 0 tfault[1] 3 r/w overcurrent timer programming bit 1 tfault[0] 2 r/w overcurrent timer programming bit 0 tdisc[1] 1 r/w load disconnect timer programming bit 1 tdisc[0] 0 r/w load disconnect timer programming bit 0 table 20b. startup, fault, and load disconnect timer values for timing register bit [1:0] (address = 16h) rstr t disc t start t fault 00 16 x t fault t disc nominal (350ms, typ) t start nominal (60ms, typ) t fault nominal (60ms, typ) 01 32 x t fault 1 / 4 x t disc nominal 1 / 2 x t start nominal 1 / 2 x t fault nominal 10 64 x t fault 1 / 2 x t disc nominal 2 x t start nominal 2 x t fault nominal 11 0 x t fault 2 x t disc nominal 4 x t start nominal 4 x t fault nominal tstart[1,0] (table 20a) programs the startup timers. startup time is the time the port is allowed to be in cur- rent limit during startup. tfault[1,0] programs the fault time. fault time is the time allowed for the port to be in current limit during normal operation. rstr[1,0] programs the discharge rate of the tfault_ counter and effectively sets the time the port remains off after an overcurrent fault. tdisc[1,0] programs the load dis- connect detection time. the device turns off power to the port if it fails to provide a minimum power mainte- nance signal for longer than the load disconnect detec- tion time (t disc ). set the bits in r16h to scale the t start , t fault , and t disc to a multiple of their nominal value specified in the electrical characteristics table. when the max5965a/max5965b shut down a port due to an extended overcurrent condition (either during startup or normal operation), if rstr_en is set high, the part does not allow the port to power back on before the restart timer (table 20b) returns to zero. this effec- tively sets a minimum duty cycle that protects the exter- nal mosfet from overheating during prolonged output overcurrent conditions. a reset sets r16h = 00h.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 37 setting cl_disc to 1 (table 21) enables port over class current protection, where the max5965a/max5965b scales down the overcurrent limit (v flt_lim ) according to the port classification status. this feature provides protection to the system against pds that violate their maximum class current allowance. the max5965 is programmed to switch to a high-power configuration and hp_time is low, the higher current set- ting is enabled only after a successful startup so that the pd powers up as a normal 15w device. if hp_time is set together with en_hp_all, the higher current setting will be active before startup. for classes 4, 5, and 6, the corresponding enable bit in register r15h must be set together with en_hp_all. in any other cases, the cur- rent level defaults to class 0. cl_disc, together with en_hp_cl_ (r15h[6:4]), en_hp_all (r15h[7]), and enx_cl6 (r1ch[7:4]) are used to program the high-power mode. see table 3 for details. setting out_iso high (table 21), forces det_ to a high-impedance state. a reset sets r17h = 0xc0. table 21. miscellaneous configurations 1 register address = 17h symbol bit r/w description int_en 7 r/w a logic-high enables int functionality rstr_en 6 r/w a logic-high enables the autorestart protection time off (as set by the rstr[1:0] bits) reserved 5 reserved reserved 4 reserved poff_cl 3 r a logic-high prevents power-up after a classification failure (i > 50ma, valid only in auto mode) cl_disc 2 r/w a logic-high enables reduced current-limit voltage threshold (v flt_lim ) according to port classification result out_iso 1 r/w forces det_ to high impedance. does not interfere with other circuit operation. hp_time 0 r/w enables high power after startup. table 22. power-enable pushbuttons register address = 19h symbol bit r/w description pwr_off4 7 w a logic-high powers off port 4 pwr_off3 6 w a logic-high powers off port 3 pwr_off2 5 w a logic-high powers off port 2 pwr_off1 4 w a logic-high powers off port 1 pwr_on4 3 w a logic-high powers on port 4 pwr_on3 2 w a logic-high powers on port 3 pwr_on2 1 w a logic-high powers on port 2 pwr_on1 0 w a logic-high powers on port 1 power-enable pushbutton for semi and manual modes is found in table 22. setting pwr_on_ to 1 turns on power to the corresponding port. setting pwr_off_ to 1 turns off power to the port. pwr_on_ is ignored when the port is already powered and during shutdown. pwr_off_ is ignored when the port is already off and during shutdown. after execution, the bits reset to 0. during detection or classification, if pwr_on_ goes high, the max5965a/max5965b gracefully terminate the current operation and turn on power to the port. the max5965a/max5965b ignore the pwr_on_ in auto mode. a reset sets r19h = 00h.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 38 ______________________________________________________________________________________ the id register (table 24) keeps track of the device id number and revision. the max5965a/max5965bs id_code[4:0] = 11001b. contact the factory for rev[2:0] value. table 23. global pushbuttons register address = 1ah symbol bit r/w description clr_int 7 w a logic-high clears all interrupts reserved 6 reserved reserved 5 reserved reset_ic 4 w a logic-high resets the max5965a/max5965b reset_p4 3 w a logic-high resets port 4 reset_p3 2 w a logic-high resets port 3 reset_p2 1 w a logic-high resets port 2 reset_p1 0 w a logic-high resets port 1 table 24. id register address = 1bh symbol bit r/w description 7 r id_code[4] 6 r id_code[3] 5 r id_code[2] 4 r id_code[1] id_code 3 r id_code[0] 2 r rev[2] 1 r rev[1] rev 0 r rev[0] writing a 1 to clr_int (table 23) clears all the event registers and the corresponding interrupt bits in regis- ter r00h. writing a 1 to reset_p_ turns off power to the corresponding port and resets only the status and event registers of that port. after execution, the bits reset to 0. writing a 1 to reset_ic causes a global software reset, after which the register map is set back to its reset state. a reset sets r1ah = 00h.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 39 enable 2-event classification for a port by setting the corre- sponding enx_cl6 bit (table 25). when the bit is enabled, the classification cycle will be repeated three times at 21.3ms intervals. the device keeps the output voltage around -9v between each cycle. the repetition of the clas- sification cycles enables discovering of class 6 pds. the enx_cl6 bit is active only in auto- or semi-mode. note: performing three consecutive classifications in manual mode is not the same as performing 2-event classification in semi or auto mode. enable the smode function (table 25) by setting en_whdog (r1fh[7]) to 1. the smode_ bit goes high when the watchdog counter reaches zero and the port(s) switch over to hardware-controlled mode. smode_ also goes high each and every time the soft- ware tries to power on a port, but is denied since the port is in hardware mode. a reset sets r1ch = 00h. table 25. smode and 2-event enable register address = 1ch symbol bit cor or r/w description en4_cl6 7 r/w port 4 2-event classification enabled en3_cl6 6 r/w port 3 2-event classification enabled en2_cl6 5 r/w port 2 2-event classification enabled en1_cl6 4 r/w port 1 2-event classification enabled smode4 3 cor port 4 hardware control flag smode3 2 cor port 3 hardware control flag smode2 1 cor port 2 hardware control flag smode1 0 cor port 1 hardware control flag table 26. watchdog register address = 1eh symbol bit r/w description 7 r/w wdtime[7] 6 r/w wdtime[6] 5 r/w wdtime[5] 4 r/w wdtime[4] 3 r/w wdtime[3] 2 r/w wdtime[2] 1 r/w wdtime[1] wdtime 0 r/w wdtime[0] set en_whdog (r1fh[7]) to 1 to enable the watchdog function. when activated, the watchdog timer counter, wdtime[7:0], continuously decrements toward zero once every 164ms. once the counter reaches zero (also called watchdog expiry), the max5965a/ max5965b enter hardware-controlled mode and each port shifts to a mode set by the hwmode_ bit in regis- ter r1fh (table 27). use software to set wdtime (table 26) and continuously set this register to some nonzero value before the register reaches zero to pre- vent a watchdog expiry. in this way, the software grace- fully manages the power to ports upon a system crash or switchover. while in hardware-controlled mode, the max5965a/ max5965b ignore all requests to turn the power on and the flag smode_ indicates that the hardware has taken control of the max5965a/max5965b operation. in addi- tion, the software is not allowed to change the mode of operation in hardware-controlled mode. a reset sets r1eh = 00h.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 40 ______________________________________________________________________________________ the clc_en enables the large capacitor detection fea- ture. when clc_en is set the device can recognize a capacitor load up to 150f. if the clc_en is reset, the max5965a/max5965b perform normal detection. ac_th allows programming of the threshold of the ac disconnect comparator. the threshold is defined as a current since the comparators verify that the peak of the current pulses sensed at the det_ input exceed a preset threshold. the current threshold is defined as follows: iac_th = 226.68a + 28.33 x nac_th where nac_th is the decimal value of ac_th. when set low, det_by inhibits port power-on if the dis- covery detection was bypassed in auto mode. when set high, det_by allows the device to turn on power to a non-ieee 802.3af load without doing detection. if oscf_rs is set high, the osc_fail bit is ignored. a reset or power-up sets r23h = 04h. default iac_th is 340a. table 27. switch mode register address = 1fh symbol bit r/w description en_whdog 7 r/w a logic-high enables the watchdog function wd_int_en 6 r/w enables interrupt on smode_ bits reserved 5 reserved reserved 4 reserved hwmode4 3 r/w port 4 switches to auto if logic-high and to shutdown if logic-low when watchdog timer expires hwmode3 2 r/w port 3 switches to auto if logic-high and to shutdown if logic-low when watchdog timer expires hwmode2 1 r/w port 2 switches to auto if logic-high and to shutdown if logic-low when watchdog timer expires hwmode1 0 r/w port 1 switches to auto if logic-high and to shutdown if logic-low when watchdog timer expires table 28. program register address = 23h symbol bit r/w description reserved 7 reserved reserved 6 reserved clc_en 5 r/w large capacitor detection enable det_by 4 r/w enables skipping detection in auto mode oscf_rs 3 r/w osc_fail reset bit 2 r/w ac_th[2] 1 r/w ac_th[1] ac_th 0 r/w ac_th[0] setting en_whdog (table 27) high activates the watchdog counter. when the counter reaches zero, the port switches to the hardware-controlled mode deter- mined by the corresponding hwmode_ bit. a low in hwmode_ switches the port into shutdown by setting the bits in register r12h to 00. a high in hwmode_ switches the port into auto mode by setting the bits in register r12h to 11. if wd_int_en is set, an interrupt is sent if any of the smode bits are set. a reset sets r1fh = 00h.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 41 table 30. miscellaneous configurations 2 address = 29h symbol bit r/w description 7 reserved 6 reserved 5 reserved 4 reserved reserved 3 reserved lsc_en 2 lsc_en 1 r/w ivee[1] ivee 0 r/w ivee[0] table 31. current-limit scaling register ivee[1:0] (address = 29h) current limit (%) 00 default 01 -5 10 -10 11 -15 table 29. high-power mode register address = 24h symbol bit r/w description reserved 7 reserved 6 r/w hp[2] 5 r/w hp[1] hp 4 r/w hp[0] 3 reserved 2 reserved 1 reserved reserved 0 reserved hp[2:0] programs the default power setting that is writ- ten upon the discovery of a class 4, 5, or 6 pd. a reset or power-up sets r24h = 00h. the ivee bits enable the current-limit scaling (table 30). this feature is used to reduce the current limit for systems running at higher voltage to maintain the desired output power. table 31 sets the current-limit scaling register. a reset or power-up sets r29h = 00h.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 42 ______________________________________________________________________________________ table 32a. icut registers 1 and 2 address = 2ah symbol bit r/w description reserved 7 reserved 6 r/w icut2[2] 5 r/w icut2[1] icut2 4 r/w icut2[0] reserved 3 reserved 2 r/w icut1[2] 1 r/w icut1[1] icut1 0 r/w icut1[0] table 32b. icut registers 3 and 4 address = 2bh symbol bit r/w description reserved 7 reserved 6 r/w icut4[2] 5 r/w icut4[1] icut4 4 r/w icut4[0] reserved 3 reserved 2 r/w icut3[2] 1 r/w icut3[1] icut3 0 r/w icut3[0] the three icut_ bits (tables 32a and 32b) allow pro- gramming of the current-limit and overcurrent thresholds in excess of the ieee 802.3af standard limit. the max5965a/max5965b can automatically set the icut register or can be manually written to by the software (see table 3). class 1 and 2 limits can also be programmed by soft- ware independently from the classification status. see table 3. a reset or power-up sets r2ah = r2bh = 00h.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 43 table 32c. icut register bit values for current-limit threshold icut_[2:0] (address = 2ah, 2bh) scale factor typical current-limit threshold (ma) 000 1x 375 001 1.5x 563 010 1.75x 656 011 2x 750 100 2.25x 844 101 2.5x 938 110 0.3x class 1 111 0.53x class 2 table 33a. classification status registers address = 2ch, 2dh, 2eh, 2fh symbol bit r/w description 7 reserved reserved 6 reserved table 33b. class sequence states cls_[5:0] (address = 2ch, 2dh, 2eh, 2fh) class sequence icut_[2:0] 000000 000 (class 0) 000 000001 001 000 000010 010 hp[2:0] 000011 011 000 000100 100 000 000101 101 hp[2:0] 000110 110 000 000111 111 (class 1) 110 001000 002 000 001001 020 011 001010 022 000 001011 200 000 001100 202 100 001101 220 000 001110 222 (class 2) 111 001111 003 000 010000 030 010 010001 033 000 010010 300 000 010011 303 010 010100 330 000 cls_[5:0] (address = 2ch, 2dh, 2eh, 2fh) class sequence icut_[2:0] 010101 333 (class 3) 000 010110 004 000 010111 040 000 011000 044 000 011001 400 000 011010 404 000 011011 440 000 011100 444 (class 4) hp[2:0] 011101 005 000 011110 050 000 011111 055 000 100000 500 000 100001 505 000 100010 550 000 100011 555 (class 5) hp[2:0] 100100 reserved 000 100101 reserved 000 100110 reserved 000 100111 reserved 000 101000 illegal 000 101001 illegal 000
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 44 ______________________________________________________________________________________ table 33b. class sequence states (continued) cls_[5:0] (address = 2ch, 2dh, 2eh, 2fh) class sequence icut_[2:0] 101010 illegal 000 101011 illegal 000 101100 illegal 000 101101 illegal 000 101110 illegal 000 101111 illegal 000 110000 reserved 000 110001 reserved 000 110010 reserved 000 110011 reserved 000 110100 reserved 000 cls_[5:0] (address = 2ch, 2dh, 2eh, 2fh) class sequence icut_[2:0] 110101 reserved 000 110110 reserved 000 110111 reserved 000 111000 reserved 000 111001 reserved 000 111010 reserved 000 111011 reserved 000 111100 reserved 000 111101 reserved 000 111110 reserved 000 111111 reserved 000 address = 30h, 31h, 32h, 33h, 34h, 35h, 36h, 37h symbol bit r/w description 7 ro ipd_[8] 6 ro ipd_[7] 5 ro ipd_[6] 4 ro ipd_[5] 3 ro ipd_[4] 2 ro ipd_[3] 1 ro ipd_[2] ipd_ 0 ro ipd_[1]/ipd_[0] table 34. current registers when the enx_cl6 (r1ch[7:4]) bits are set, 2-event classification is enabled. classification is repeated three times and the classification results are set according to table 33b. a class 6 pd is defined by any sequence of the type [00x, 0x0, 0xx, x00, x0x, xx0] where x can be 1, 2, 3, 4, or 5. all sequences made by the same class result define the class itself (for example, 222 defines class 2). any other sequence will be considered illegal and coded as 101xxx. for example, a sequence 232 or 203 will be illegal. the illegal sequences all default to class 0. a reset or power-up sets r2ch = r2dh = r2eh = r2fh = 00h. the max5965a/max5965b provide current readout for each port during classification and normal power mode. the current per port information is separated into 9 bits. they are organized into two consecutive registers for each one of the ports. the information can be quickly retrieved using the autoincrement option of the address pointer. to avoid the lsb register chang- ing while reading the msb, the information is frozen once the addressing byte points to any of the current readout registers. during power mode, the current value can be calculat- ed as i port = n ipd_ x 2ma during classification, the current is i class = n ipd_ x 0.0975ma where n ipd_ is the decimal value of the 9-bit word. the adc saturates both at full scale and at zero. a reset sets r30h to r37h = 00h.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 45 addr register name r/w port bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state interrupts 00h interrupt ro g sup_flt tstr_flt imax_flt cl_end det_end ld_disc pg_int pen_int 0000,0000 01h interrupt mask r/w g mask7 mask6 mask5 mask4 mask3 mask2 mask1 mask0 aaa0,0a00 events 02h power event ro 4321 0000,0000 03h power event cor cor pg_chg4 pg_chg3 pg_chg2 pg_chg1 pwen_ chg4 pwen_ chg3 pwen_ chg2 pwen_ chg1 04h detect event ro 4321 0000,0000 05h detect event cor cor cl_end4 cl_end3 cl_end2 cl_end1 det_end4 det_end3 det_end2 det_end1 06h fault event ro 4321 0000,0000 07h fault event cor cor ld_disc4 ld_disc3 ld_disc2 ld_disc1 imax_flt4 imax_flt3 imax_flt2 imax_flt1 08h startup event ro 4321 0000,0000 09h startup event cor cor ivc4 ivc3 ivc2 ivc1 strt_flt4 strt_flt3 strt_flt2 strt_flt1 0ah supply event ro 4321 0bh supply event cor cor tsd v dd_ov v dd_uv v ee_uvlo v ee_ov v ee_uv osc_fail v dd_uvlo status 0ch port 1 status ro 1 reserved cls1[2] cls1[1] cls1[0] reserved d et_s t1[ 2] det_st1[1] det_st1[0] 0000,0000 0dh port 2 status ro 2 reserved cls2[2] cls2[1] cls2[0] reserved d et_s t2[ 2] det_st2[1] det_st2[0] 0000,0000 0eh port 3 status ro 3 reserved cls3[2] cls3[1] cls3[0] reserved d et_s t3[ 2] det_st3[1] det_st3[0] 0000,0000 0fh port 4 status ro 4 reserved cls4[2] cls4[1] cls4[0] reserved d et_s t4[ 2] det_st4[1] det_st4[0] 0000,0000 10h power status ro 4321 pgood4 pgood3 pgood2 pgood1 pwr_en4 pwr_en3 pwr_en2 pwr_en1 0000,0000 11h address input status ro g reserved reserved a3 a2 a1 a0 midspan auto 00a3a2, a1a0ma configuration 12h operating mode r/w 4321 p4_m1 p4_m0 p3_m1 p3_m0 p2_m1 p2_m0 p1_m1 p1_m0 aaaa,aaaa 13h load disconnect detection enable r/w 4321 acd_en4 acd_en3 acd_en2 acd_en1 dcd_en4 dcd_en3 dcd_en2 dcd_en1 0000,aaaa 14h detection and classification enable r/w 4321 class_en4 class_en3 class_en2 class_en1 det_en4 det_en3 det_en2 det_en1 aaaa,aaaa 15h backoff and high- power enable r/w 4321 en_hp_all en_hp_cl6 en_hp_cl5 en_ hp_cl4 bckoff4 bckoff3 bckoff2 bckoff1 0000,xxxx 16h timing configuration r/w g rstr[1] rstr[0] tstart[1] tstart[0] tfault[1] tfault[0] tdisc[1] tdisc[0] 0000,0000 17h miscellaneous configuration 1 r/w g int_en rstr_en reserved reserved poff_cl cl_disc out_iso hp_time 1100,0000 pushbuttons 18h reserved r/w g reserved reserved reserved reserved reserved reserved reserved reserved 19h power enable wo 4321 pwr_off4 pwr_off3 pwr_off2 pwr_off1 pwr_on4 pwr_on3 pwr_on2 pwr_on1 0000,0000 1ah global wo g clr_int reserved reserved reset_ic reset_p4 reset_p3 reset_p2 reset_p1 0000,0000 general 1bh id ro g id_code[4] id_code[3] id_code[ 2] id_code[ 1] id_ code[ 0] rev[2] rev[1] rev[0] 1100,0000 1ch smode and 2-event enable cor or r/w 4321 en4_cl6 en3_cl6 en2_cl6 en1_cl6 smode4 smode3 smode2 smode1 0000,0000 1dh reserved g reserved reserved reserved reserved reserved reserved reserved reserved 1eh watchdog r/w g wdtime[7] wdtime[6] wdtime[5] wdtime[4] wdtime[3] wdtime[2] wdtime[1] wdtime[0] 0000,0000 1fh switch mode r/w 4321 en_ whdog wd_int_en reserved reserved hwmode4 hwmode3 hwmode2 hwmode1 0000,0000 table 35. register summary
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 46 ______________________________________________________________________________________ addr register name r/w port bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state maxim reserved 20h reserved g reserved reserved reserved reserved reserved reserved reserved reserved 21h reserved g reserved reserved reserved reserved reserved reserved reserved reserved 22h reserved g reserved reserved reserved reserved reserved reserved reserved reserved 23h program r/w 4321 reserved reserved clc_en det_by oscf_rs ac_th[2] ac_th[1] ac_th[0] 24h high-power mode r/w g reserved hp[2] hp[1] hp[0] reserved reserved reserved reserved 0000,0000 25h reserved g reserved reserved reserved reserved reserved reserved reserved reserved 0000,0000 26h reserved g reserved reserved reserved reserved reserved reserved reserved reserved 0000,0000 27h reserved g reserved reserved reserved reserved reserved reserved reserved reserved 28h reserved g reserved reserved reserved reserved reserved reserved reserved reserved 29h miscellaneous configuration 2 r/w 1234 reserved reserved reserved reserved reserved lsc_en ivee[1] ivee[0] 0000,0000 2ah icu t regi ster s 1 and 2 r/w 21 reserved icut2[2] icut2[1] icut2[0] reserved icut1[2] icut1[1] icut1[0] 0000,0000 2bh icu t regi ster s 3 and 4 r/w 43 reserved icut4[2] icut4[1] icut4[0] reserved icut3[2] icut3[1] icut3[0] 0000,0000 classification status registers 2ch port 1 class ro 1 reserved reserved cls1[5] cls1[4] cls1[3] cls1[2] cls1[1] cls1[0] 0000,0000 2dh port 2 class ro 2 reserved reserved cls2[5] cls2[4] cls2[3] cls2[2] cls2[1] cls2[0] 0000,0000 2eh port 3 class ro 3 reserved reserved cls3[5] cls3[4] cls3[3] cls3[2] cls3[1] cls3[0] 0000,0000 2fh port 4 class ro 4 reserved reserved cls4[5] cls4[4] cls4[3] cls4[2] cls4[1] cls4[0] 0000,0000 current register 30h current port 1 (msb) ro 1 ipd1[8] ipd1[7] ipd1[6] ipd1[5] ipd1[4] ipd1[3] ipd1[2] ipd1[1] 0000,0000 31h current port 1 (lsb) ro 1 reserved reserved reserved reserved reserved reserved reserved ipd1[0] 0000,0000 32h current port 2 (msb) ro 2 ipd2[8] ipd2[7] ipd2[6] ipd2[5] ipd2[4] ipd2[3] ipd2[2] ipd2[1] 0000,0000 33h current port 2 (lsb) ro 2 reserved reserved reserved reserved reserved reserved reserved ipd2[0] 0000,0000 34h current port 3 (msb) ro 3 ipd3[8] ipd3[7] ipd3[6] ipd3[5] ipd3[4] ipd3[3] ipd3[2] ipd3[1] 0000,0000 35h current port 3 (lsb) ro 3 reserved reserved reserved reserved reserved reserved reserved ipd3[0] 0000,0000 36h current port 4 (msb) ro 4 ipd4[8] ipd4[7] ipd4[6] ipd4[5] ipd4[4] ipd4[3] ipd4[2] ipd4[1] 0000,0000 37h current port 4 (lsb) ro 4 reserved reserved reserved reserved reserved reserved reserved ipd4[0] 0000,0000 table 35. register summary (continued) * uv and uvlo bits of v ee and v dd asserted depends on the order v ee and v dd supplies are brought up. a = auto pin state before reset. m = midspan state before reset. a3...0 = address input states before reset.
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 47 max5965a max5965b -48v gate_ internal pulldown (manual mode) 100 ? -48vrtn fdt3612 100v, 120m ? sot-223 sense_ v ee out_ off on det_ sdain sdaout scl dgnd v dd a0 a1 a2 a3 osc auto midspan agnd internal pulldown (signal mode) 0.5 ? 1% 1n4448 1k ? 1 of 4 channels 1.8v to 5v, (ref to dgnd) int reset 3k ? 3k ? 180 ? 180 ? 180 ? optional buffer internal 50k ? pullup 4.7k ? 1k ? v dd 1n4002 hpcl063l optional buffer optional buffer hpcl063l hpcl063l vccrtn v cc (3.3v) scl sda serial interface 3k ? 3k ? isolation 0.47 f 100v shd_ sine wave 100hz 10% peak amplitude 2.2v 0.1v valley amplitude 0.2v 0.1v smbj 58ca 0.1 f 2.2m ? -48vout 8 7 5 4 6 3 2 1 -48vout 0.1 f 0.1 f 0.1 f 0.1 f 75 ? 75 ? 75 ? 75 ? 1000pf 250vac 24 22 21 19 23 20 rx1+ rx1- tx1+ tx1- rxt1 txct1 rd1+ rd1- td1+* *use halo tg111-hrpe40ny or pulse hx6015nl for high power td1- 1 3 4 5 phy 1/2 of h2005a rj?5 connector applications information figure 13. poe system diagram with lan transformer
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 48 ______________________________________________________________________________________ max5965a max5965b -48v gate_ internal pulldown (manual mode) 100 ? -48vrtn fdt3612 100v, 120m ? sot-223 sense_ v ee out_ off on det_ sdain sdaout scl dgnd v dd a0 a1 a2 a3 osc auto midspan agnd internal pulldown (signal mode) 0.5 ? 1% 1n4448 1k ? 1 of 4 channels 1.8v to 5v (ref to dgnd) int reset 3k ? 3k ? 180 ? 180 ? 180 ? optional buffer internal 50k ? pullup 4.7k ? 1k ? v dd 1n4002 hpcl063l optional buffer optional buffer hpcl063l hpcl063l vccrtn v cc (3.3v) scl sda serial interface 3k ? 3k ? isolation 0.47 f 100v shd_ sine wave 100hz 10% peak amplitude 2.2v 0.1v valley amplitude 0.2v 0.1v smbj 58ca 0.1 f 2.2m ? -48vout 8 7 5 4 6 3 2 1 rj?5 connector -48vout data figure 14. poe system diagram
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 49 gnd -48v -48v gnd c6 0.47 f 100v r10 2 ? r6 1 ? c3 15nf q4 mmbta56 r5 1k ? l1 68 h, do3308p-683 max5020 1 2 3 4 8 7 6 5 v+ v dd fb v cc ndrv gnd cs c2 0.022 f r8 30 ? c1 0.1 f c8 2.2 f r4 1 ? r9 1 ? gate source drain q1 si2328 ds c9 4.7nf c7 0.22 f r7 1.02k ? r2 6.81k ? r3 2.61k ? q3 mmbta56 d1 diodes inc.: b1100 c4 220 f sanyo 6svpa220maa r1 2.61k ? q2 mmbta56 c5 4.7 f +3.3v +3.3v gnd 300ma ss_shdn figure 15. -48v to +3.3v (300ma) boost converter solution for v dig 1700 (mils) 965 (mils) 1700 (mils) 965 (mils) 1700 (mils) 965 (mils) figure 16. layout example for boost converter solution for v dig
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 50 ______________________________________________________________________________________ component list for v dig supply designation description c1 0.1f, 25v ceramic capacitor c2 0.022f, 25v ceramic capacitor c3 15nf, 25v ceramic capacitor c4 220f capacitor sanyo 6svpa220maa c5 4.7f, 16v ceramic capacitor c6 0.47f, 100v ceramic capacitor c7 0.22f, 16v ceramic capacitor c8 2.2f, 16v ceramic capacitor c9 4.7nf, 16v ceramic capacitor d1 b1100 100v schottky diode l1 68h inductor coilcraft do3308p-683 or equivalent designation description q1 si2328ds vishay n-channel mosfet, sot23 q2, q3, q4 mmbta56 small-signal pnp r1, r3 2.61k ? 1% resistors r2 6.81k ? 1% resistor r4, r6, r9 1 ? 1% resistors r5 1k ? 1% resistor r7 1.02k ? 1% resistor r8 30 ? 1% resistor r10 2 ? 1% resistor u1 high-voltage pwm ic max5020esa (8-pin so)
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 51 typical operating circuits max5965a max5965b -48v gate_ internal pulldown (manual mode) 100 ? -48vrtn fdt3612 100v, 120m ? sot-223 sense_ v ee out_ off on det_ sdain sdaout scl dgnd v dd a0 a1 a2 a3 osc auto midspan agnd internal pulldown (signal mode) 0.5 ? 1% -48v output to port -48v rtn output to port note: all signal pins are referenced to dgnd. dgnd range is between v ee and (agnd + 4v). 1n4448 1 of 4 channels 1.8v to 3.7v, (ref to dgnd) int reset 3k ? 3k ? 180 ? 180 ? 180 ? optional buffer internal 50k ? pullup 4.7k ? 1k ? v dd can be up to 100k ? hpcl063l optional buffer optional buffer hpcl063l hpcl063l vccrtn v cc (3.3v) scl sda serial interface 3k ? 3k ? isolation n.c. shd_ typical operating circuit 1 (without ac load removal detection)
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet 52 ______________________________________________________________________________________ typical operating circuits (continued) max5965a max5965b -48v gate_ internal pulldown (manual mode) 100 ? -48vrtn fdt3612 100v, 120m ? sot-223 sense_ v ee out_ off on det_ sdain sdaout scl dgnd v dd a0 a1 a2 a3 osc auto midspan agnd internal pulldown (signal mode) 0.5 ? 1% -48v output to port -48v rtn output to port note: all signal pins are referenced to dgnd. dgnd range is between v ee and (agnd + 4v). 1n4448 1 of 4 channels 1.8v to 3.7v, (ref to dgnd) int reset 3k ? 3k ? 180 ? 180 ? 180 ? optional buffer internal 50k ? pullup 4.7k ? 1k ? v dd can be up to 100k ? hpcl063l optional buffer optional buffer hpcl063l hpcl063l vccrtn v cc (3.3v) scl sda serial interface 3k ? 3k ? isolation n.c. shd_ typical operating circuit 2 (without ac load removal detection); alternative dgnd connection
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet ______________________________________________________________________________________ 53 typical operating circuits (continued) max5965b -48v gate_ internal pulldown (manual mode) 100 ? -48vrtn fdt3612 100v, 120m ? sot-223 sense_ v ee out_ off on det_ sdain sdaout scl dgnd v dd a0 a1 a2 a3 osc auto midspan agnd internal pulldown (signal mode) 0.5 ? 1% -48v output to port -48v rtn output to port note: all signal pins are referenced to dgnd. 1n4448 1k ? 1 of 4 channels 1.8v to 3.7v, (ref to dgnd) int reset 3k ? 3k ? 180 ? 180 ? 180 ? optional buffer internal 50k ? pullup 4.7k ? 1k ? v dd 1n4002 can be up to 100k ? hpcl063l optional buffer optional buffer hpcl063l hpcl063l vccrtn v cc (3.3v) scl sda serial interface 3k ? 3k ? isolation dgnd must be connected directly to agnd for ac disconnect detection circuit to operate. 0.47 f 100v shd_ sine wave 100hz 10% peak amplitude 2.2v 0.1v valley amplitude 0.2v 0.1v typical operating circuit 3 (with ac load removal detection) chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 36 ssop a36+4 21-0040 90-0096
max5965a/max5965b high-power, quad, monolithic, pse controllers for power over ethernet maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidanc e. 54 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/09 initial release 1 1/10 revised features , register map and description section, and tables 32 and 37. 1, 37, 41, 45 2 5/11 removed "pre-" from ieee standard, updated typical operating characteristics , and text throughout the data sheet. 1, 8C12, 15, 18, 22, 31, 40C47 3 3/12 corrected power mode formula. 44

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